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| m68hc05 microcontrollers freescale.com MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet MC68HC705KJ1 rev. 4.1 07/2005
MC68HC705KJ1 ? mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 3 freescale? and the freescale logo are trade marks of freescale semiconductor, inc. ? freescale semiconductor, inc., 2005. all rights reserved. mc68hc705jk1 mc68hrc705kj1 mc68hlc705kj1 data sheet to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com revision history MC68HC705KJ1 ? mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 4 freescale semiconductor the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history date revision level description page number(s) april, 2002 3.0 figure 1-4. crystal connections with oscillator internal resistor mask option ? changed pa7 designator to osc1 in two places 17 figure 1-5. crystal connections without oscillator internal resistor mask option ? changed pa7 designator to osc1 in two places 17 figure 1-6. ceramic resonator connections with oscillator internal resistor mask option ? changed pa7 designator to osc1 in two places 18 figure 1-7. ceramic resonator connections without oscillator internal resistor mask option ? changed pa7 designator to osc1 in two places 18 figure 1-8. external clock connections ? changed pa7 designator to osc1 in two places 19 figure b-1. crystal connections ? added osc2 designation 105 table b-3. mc68hlc705kj1 (low frequency) order numbers ? corrected table title 106 may, 2003 4.0 reformatted to new publications standards. throughout figure a-2. typical internal operating frequency for various vdd at 25 c ? rc oscillator option only ? replaced graph 102 july, 2005 4.1 updated to meet freescale identity guidelines. throughout MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 5 list of chapters chapter 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 chapter 2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 chapter 3 computer operating properly module (cop) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 chapter 4 central processor unit (cpu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 chapter 5 external interrupt module (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 chapter 6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 chapter 7 parallel i/o ports (p orts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 chapter 8 resets and interr upts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 chapter 9 multifunction timer module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 chapter 10 electrical spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 chapter 11 ordering information and mechanical specifications . . . . . . . . . . . . . . . . . . . 97 appendix a mc68hrc705kj1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 appendix b mc68hlc705kj1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 list of chapters MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 6 freescale semiconductor MC68HC705KJ1 ? mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 7 table of contents chapter 1 introduction 1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.3 programmable options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4.2 osc1 and osc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4.2.1 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4.2.2 ceramic resonator oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.4.2.3 rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4.2.4 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.4.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.4.4 irq /v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.4.5 pa0?pa7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.4.6 pb2 and pb3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 chapter 2 memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.5 input/output register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.6 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.7 eprom/otprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.7.1 eprom/otprom programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.7.2 eprom programming register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.7.3 eprom erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.8 mask option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.9 eprom programming characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 chapter 3 computer operating properly module (cop) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.1 cop watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.2 cop watchdog timeout period. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.3 clearing the cop watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table of contents MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 8 freescale semiconductor 3.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5 cop register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.6.1 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.6.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 chapter 4 central processor unit (cpu) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.3 cpu control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4 arithmetic/logic unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.5 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.5.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.5.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.5.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.5.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.5.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.6 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.6.1 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.6.1.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.6.1.2 immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.6.1.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.6.1.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.6.1.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.6.1.6 indexed, 8-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.6.1.7 indexed, 16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.6.1.8 relative. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.6.2 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.6.2.1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.6.2.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 4.6.2.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.6.2.4 bit manipulation instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.6.2.5 control instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.6.3 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.7 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 chapter 5 external interrupt module (irq) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.3.1 irq /v pp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 5.3.2 optional external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.4 irq status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.5 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 9 chapter 6 low-power modes 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.2 exiting stop and wait modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3 effects of stop and wait modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.1 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.1.1 stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.1.2 wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.2 cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.2.1 stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.2.2 wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.3 cop watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.3.1 stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.3.2 wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.4 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.4.1 stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.4.2 wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.5 eprom/otprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.5.1 stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.5.2 wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.4 data-retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.5 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 chapter 7 parallel i/o ports (ports) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.2.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.2.2 data direction register a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.2.3 pulldown register a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.2.4 port led drive capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.2.5 port a i/o pin interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.3.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.3.2 data direction register b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.3.3 pulldown register b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.4 i/o port electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 chapter 8 resets and interrupts 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.2 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.2.1 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.2.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.2.3 cop watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table of contents MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 10 freescale semiconductor 8.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.3.1 software interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.3.2 external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.3.3 timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.3.3.1 real-time interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.3.3.2 timer overflow interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.3.4 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 chapter 9 multifunction timer module 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.5 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 9.5.1 timer status and control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 9.5.2 timer counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.6.1 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.6.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 chapter 10 electrical specifications 10.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.2 operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.4 power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 10.5 5.0-v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.6 3.3-v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.7 driver characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.8 typical supply currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.9 eprom programming characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.10 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 chapter 11 ordering information and m echanical specifications 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.2 mcu order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.3 16-pin pdip ? case #648 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.4 16-pin soic ? case #751g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.5 16-pin cerdip ? case #620a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 11 appendix a mc68hrc705kj1 a.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 a.2 rc oscillator connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 a.3 typical internal operating frequency for rc oscillator op tion . . . . . . . . . . . . . . . . . . . . . . . . 102 a.4 rc oscillator connections (no external resistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 a.5 typical internal operating frequency versus tem perature (no external resistor) . . . . . . . . 104 a.6 package types and order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 appendix b mc68hlc705kj1 b.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 b.2 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 b.3 package types and order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table of contents MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 12 freescale semiconductor MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 13 chapter 1 introduction 1.1 features features on the MC68HC705KJ1 include: robust noise immunity 4.0-mhz internal operating frequency at 5.0 v 1240 bytes of eprom/otprom (electricall y programmable read-only memory/one-time programmable read-only memory), including eight bytes for user vectors 64 bytes of user ram peripheral modules: ? 15-stage multifunction timer ? computer operating properly (cop) watchdog 10 bidirectional input/out put (i/o) lines, including: ? 10-ma sink capability on all i/o pins ? software programmable pulldowns on all i/o pins ? keyboard scan with selectable interrupt on four i/o pins ? 5.5-ma source capability on six i/o pins selectable sensitivity on external interrupt ( edge- and level-sensitive or edge-sensitive only) on-chip oscillator with connections for: ?crystal ? ceramic resonator ? resistor-capacitor (rc) oscillator (mc68hrc 705kj1) with or without external resistor ? external clock ? low-speed (32-khz) crystal (mc68hlc705kj1) memory-mapped i/o registers fully static operation with no minimum clock speed power-saving stop, halt, wait, and data-retention modes external interrupt mask bit and acknowledge bit illegal address reset internal steering diode and pullup resistor from reset pin to v dd selectable eprom security (1) selectable oscillator bias resistor 1. no security feature is absolutely secu re. however, freescale?s strategy is to make reading or copying the eprom/otprom difficult for unauthorized users. introduction MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 14 freescale semiconductor 1.2 structure figure 1-1. block diagram 0000000011 watchdog and illegal address detect static ram (sram) ? 64 bytes alu cpu control 68hc05 cpu accumulator index register stk ptr program counter condition code register 15-stage multifunction timer system divide internal oscillator osc1 osc2 cpu registers user eprom ? 1240 bytes mask option register (mor) 10-ma sink capabili ty on all i/o pins data direction register a data direction register b port a port b pb3 (1) pb2 (1) pa7 pa6 pa5 pa4 pa3 (1) (2) pa2 (1) (2) pa1 (1) (2) pa0 (1) (2) reset irq /v pp 111hinzc by 32 notes: 1. 5.5 ma source capability 2. external interrupt capability programmable options MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 15 1.3 programmable options the options in table 1-1 are programmable in the mask option register. 1.4 pin functions pin assignments are shown in figure 1-2 with the functions described in the following subsections. figure 1-2. pin assignments table 1-1. programmable options feature option cop watchdog timer enabled or disabled external interrupt triggering edge-sensitive only or edge- and level-sensitive port a irq pin interrupts enabled or disabled port pulldown resistors enabled or disabled stop instruction mode stop mode or halt mode crystal oscillator internal resistor enabled or disabled eprom security enabled or disabled short oscillator delay counter enabled or disabled reset 1 osc1 2 osc2 3 pb3 4 pb2 5 v dd 6 v ss 7 pa7 8 irq /v pp 16 pa0 15 pa1 14 pa2 13 pa3 12 pa4 11 pa5 10 pa6 9 introduction MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 16 freescale semiconductor 1.4.1 v dd and v ss v dd and v ss are the power supply and ground pins. th e mcu operates from a single power supply. very fast signal transitions occur on the mcu pins, placing high, short-durati on current demands on the power supply. to prevent noise problems, take special care, as figure 1-3 shows, by placing the bypass capacitors as close as possible to the mcu. c2 is an optional bulk cu rrent bypass capacitor for use in applications that require the port pins to source high current levels. figure 1-3. bypassing layout recommendation 1.4.2 osc1 and osc2 the osc1 and osc2 pins are the connections for the on-chip oscillator. the oscillator can be driven by any of the following: 1. standard crystal (see figure 1-4 and figure 1-5 .) 2. ceramic resonator (see figure 1-6 and figure 1-7 .) 3. resistor/capacitor (rc) oscillator (refer to appendix a mc68hrc705kj1 .) 4. external clock signal as shown in (see figure 1-8 .) 5. low speed (32 khz) crystal connections (refer to appendix b mc68hlc705kj1 .) the frequency, f osc , of the oscillator or external clock source is divided by two to produce the internal operating frequency, f op . 1.4.2.1 crystal oscillator figure 1-4 and figure 1-5 show a typical crystal oscillator circuit fo r an at-cut, parallel resonant crystal. follow the crystal supplier?s recommendations, as the crystal parameters determine the external component values required to provide reliable startup and maximum stability. the load capacitance values used in the oscillator circuit design should include all stray layout capacitances. to minimize output distortion, mount the crystal and capacitors as close as po ssible to the pins. an internal startup resistor of approximately 2 m ? is provided between osc1 and osc2 for the crystal oscillator as a programmable mask option. note use an at-cut crystal and not an at-strip crystal because the mcu can overdrive an at-strip crystal. c1 c2 mcu c1 0.1 f c2 v+ + v dd v ss v dd v ss pin functions MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 17 figure 1-4. crystal connections with oscillator internal resistor mask option figure 1-5. crystal connections without oscillator internal resistor mask option 1.4.2.2 ceramic resonator oscillator to reduce cost, use a ceramic resonator inste ad of the crystal. the circuits shown in figure 1-6 and figure 1-7 show ceramic resonator circuits. follow the resonator manufacturer?s recommendations, as the resonator parameters determine the external component values required for maximum stability and reliable starting. the load capacitance values used in the oscillator circuit design should include all stray capacitances. mount the resonator and components as close as possibl e to the pins for startup stabilization and to minimize output distortion. an internal startup resistor of approximately 2 m ? is provided between osc1 and osc2 as a programmable mask option. mcu c1 c2 xtal c4 c3 xtal c3 27 pf c4 27 pf osc1 osc2 osc1 osc2 v ss v dd v ss mcu c1 c2 r xtal c4 c3 r 10 m ? xtal c3 27 pf c4 27 pf osc1 osc2 v dd v ss osc1 osc2 v ss introduction MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 18 freescale semiconductor figure 1-6. ceramic resonator connections with oscillator internal resistor mask option figure 1-7. ceramic resonator connections without oscillator internal resistor mask option 1.4.2.3 rc oscillator refer to appendix a mc68hrc705kj1 . mcu c1 c2 ceramic c4 c3 ceramic c3 27 pf c4 27 pf resonator resonator osc1 osc2 osc1 osc2 v dd v ss v ss mcu c1 c2 r ceramic c4 c3 r 10 m ? ceramic c3 27 pf c4 27 pf resonator resonator v ss v dd v ss osc1 osc2 osc1 osc2 pin functions MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 19 1.4.2.4 external clock an external clock from another cmos-compatible dev ice can be connected to the osc1 input, with the osc2 input not connected, as shown in figure 1-8 . this configuration is possible regardless of whether the crystal/ceramic resonator or the rc oscillator is enabled. figure 1-8. external clock connections 1.4.3 reset applying a logic 0 to the reset pin forces the mcu to a known startup state. an internal reset also pulls the reset pin low. an internal resistor to v dd pulls the reset pin high. a steering diode between the reset and v dd pins discharges any reset pin voltage when power is removed from the mcu. the reset pin contains an internal schmitt trigger to im prove its noise immunity as an input. refer to chapter 8 resets and interrupts for more information. 1.4.4 irq /v pp the external interrupt/programming voltage pin (irq /v pp ) drives the asynchronous irq interrupt function of the cpu. additionally, it is used to program the user eprom and mask option register. (see chapter 2 memory and chapter 5 external interrupt module (irq) .) the level bit in the mask option register provi des negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive tr iggering for the interrupt function. if level-sensitive triggering is selected, the irq /v pp input requires an external resistor to v dd for wired-or operation. if the irq /v pp pin is not used, it must be tied to the v dd supply. the irq /v pp pin contains an internal schmitt trigger as pa rt of its input to impr ove noise immunity. the voltage on this pin should not exceed v dd except when the pin is being used for programming the eprom. note the mask option register can enable the pa0 ? pa3 pins to function as external interrupt pins. 1.4.5 pa0?pa7 these eight input/output (i/o) lines comprise port a, a general-purpose bidirectional i/o port. (see chapter 5 external interrupt module (irq) for information on pa0?pa3 external interrupts.) 1.4.6 pb2 and pb3 these two i/o lines comprise port b, a general-purpose bidirectional i/o port. mcu external cmos clock osc1 osc2 introduction MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 20 freescale semiconductor MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 21 chapter 2 memory 2.1 introduction this section provides: memory map ( figure 2-1 ) summary of the input/output registers ( figure 2-2 ) description of: ? random-access memory (ram) ? eprom/otprom (electrically programmabl e read-only memory/one-time programmable read-only memory) ? mask option register memory features include: 1232 bytes of user eprom, plus eight bytes for user vectors 64 bytes of user ram 2.2 unimplemented memory locations accessing an unimplemented location can have unpredictable effects on mcu operation. in figure 2-2 and in register figures in this document, unimplemented locations are shaded. 2.3 reserved memory locations accessing a reserved location can have unpredictable effects on mcu operation. in figure 2-2 and in register figures in this document, reserved locations are marked with the word reserved or with the letter r. 2.4 memory map see figure 2-1 . memory MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 22 freescale semiconductor port a data register (porta) $0000 port b data register (portb) $0001 unimplemented $0002 $0003 data direction register a (ddra) $0004 data direction register b (ddrb) $0005 unimplemented $0006 $0007 timer status and control register (tscr) $0008 timer control register (tcr) $0009 $0000 i/o registers 32 bytes irq status and control register (iscr) $000a unimplemented $000b $001f $0020 unimplemented 160 bytes $000f pulldown register port a (pdra) $0010 $00bf pulldown register port b (pdrb) $0011 $00c0 ram 64 bytes unimplemented $0012 $00ff $0017 $0100 unimplemented 512 bytes eprom programming register (eprog) $0018 unimplemented $0019 $02ff $0300 eprom 1232 bytes $001e reserved $001f $07cf $07d0 unimplemented 30 bytes cop register (copr) (1) $07f0 mask option register (mor) $07f1 $07ed reserved $07f2 $07ee test rom 2 bytes $07ef $07f7 $07f0 registers and eprom 16 bytes timer interrupt vector high $07f8 timer interrupt vector low $07f9 $07ff external interrupt vector high $07fa external interrupt vector low $07fb software interrupt vector high $07fc software interrupt vector low $07fd reset vector high $07fe reset vector low $07ff note 1. writing to bit 0 of $07f0 clears the cop watchdog. figure 2-1. memory map input/output register summary MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 23 2.5 input/output register summary addr.register name bit 7654321bit 0 $0000 port a data register (porta) see page 64. read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset $0001 port b data register (portb) see page 66. read: 0 0 refer to chapter 7 paral- lel i/o ports (ports) pb3 pb2 refer to chapter 7 paral- lel i/o ports (ports) write: reset: unaffected by reset $0002 unimplemented $0003 unimplemented $0004 data direction register a (ddra) see page 64. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 67. read: 0 0 refer to chapter 7 paral- lel i/o ports (ports) ddrb3 ddrb2 refer to chapter 7 paral- lel i/o ports (ports) write: reset:00000000 $0006 unimplemented $0007 unimplemented $0008 timer status and control register (tscr) see page 81. read: tof rtif toie rtie 00 rt1 rt0 write: tofr rtifr reset:00000011 $0009 timer counter register (tcr) see page 82. read: tcr7 tcr6 tcr5 tc r4 tcr3 tcr2 tcr1 tcr0 write: reset:00000000 $000a irq status and control reg- ister (iscr) see page 54. read: irqe 000irqf000 write: r irqr reset:10000000 = unimplemented r = reserved u = unaffected figure 2-2. i/o register summary (sheet 1 of 2) memory MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 24 freescale semiconductor $000b unimplemented $000f unimplemented $0010 pulldown register port a (pdra) see page 65. read: write: pdia7 pdia6 pdia5 pdia4 pdia3 pdia2 pdia1 pdia0 reset:00000000 $0011 pulldown register port b (pdrb) see page 68. read: write: refer to chapter 7 paral- lel i/o ports (ports) pdib3 pdib2 refer to chapter 7 paral- lel i/o ports (ports) reset:00000000 $0012 unimplemented $0017 unimplemented $0018 eprom programming register (eprog) see page 26. read:00000 elat mpgm epgm write: rrrr reset:00000000 $0019 unimplemented $001e unimplemented $001f reserved rrrrrrrr $07f0 cop register (copr) see page 30. read: write: copc reset:uuuuuuu0 $07f1 mask option register (mor) see page 27. read: soscd epmsec oscres swait pdi pirq level copen write: reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. i/o register summary (sheet 2 of 2) ram MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 25 2.6 ram the 64 addresses from $00c0 to $00ff serve as both the user ram and the stack ram. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements when the cpu stores a byte on the stack and increments when the cpu retrieves a byte from the stack. note be careful when using nested subroutines or multiple interrupt levels. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. 2.7 eprom/otprom an mcu with a quartz window has 1240 bytes of erasable, programmable ro m (eprom). the quartz window allows eprom erasure with ultraviolet light. note keep the quartz window covered with an opaque material except when erasing the mcu. ambient li ght can affect mcu operation. in an mcu without the quartz window, the eprom cannot be erased and serves as 1240 bytes of one-time programmable rom (otprom). the following addresses are us er eprom/otprom locations: $0300?$07cf $07f8?$07ff, used for user-defined interrupt and reset vectors the cop register (copr) is an eprom /otprom location at address $07f0. the mask option register (mor) is an eprom/otprom location at address $07f1. 2.7.1 eprom/otprom programming the two ways to program the eprom/otprom are: manipulating the control bits in the eprom programming register to program the eprom/otprom on a byte-by-byte basis programming the eprom/otprom with the m68 hc705j in-circuit simulator (m68hc705jics) available from freescale memory MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 26 freescale semiconductor 2.7.2 eprom programming register the eprom programming register (eprog) contai ns the control bits for programming the eprom/otprom. elat ? eprom bus latch bit this read/write bit latches the address and data buses for eprom/otprom programming. clearing the elat bit automatically clears the epgm bit. eprom/otprom data cannot be read while the elat bit is set. reset clears the elat bit. 1 = address and data buses configured fo r eprom/otprom programming the eprom 0 = address and data buses configured for normal operation mpgm ? mor programming bit this read/write bit applies programming power from the irq /v pp pin to the mask option register. reset clears mpgm. 1 = programming voltage applied to mor 0 = programming voltage not applied to mor epgm ? eprom programming bit this read/write bit applies the voltage from the irq /v pp pin to the eprom. to write the epgm bit, the elat bit must be set already. reset clears epgm. 1 = programming voltage (irq /v pp pin) applied to eprom 0 = programming voltage (irq /v pp pin) not applied to eprom note writing logic 1s to both the elat and epgm bits with a single instruction sets elat and clears epgm. elat must be set first by a separate instruction. bits [7:3] ? reserved take the following steps to pr ogram a byte of eprom/otprom: 1. apply the programming voltage, v pp , to the irq /v pp pin. 2. set the elat bit. 3. write to any eprom/otprom address. 4. set the epgm bit and wait for a time, t epgm . 5. clear the elat bit. 2.7.3 eprom erasing the erased state of an eprom bit is logic 0. erase the eprom by exposing it to 15 ws/cm 2 of ultraviolet light with a wavelength of 2537 angstroms. position the ultraviolet light source one inch from the eprom. do not use a shortwave filter. address: $0018 bit 7654321bit 0 read:00000 elat mpgm epgm write: rrrr reset:00000000 = unimplemented r = reserved figure 2-3. eprom programming register (eprog) mask option register MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 27 2.8 mask option register the mask option register (mor) is an eprom/ot prom byte that controls the following options: cop watchdog (enable or disable) external interrupt pin triggering (edge-s ensitive only or edge- and level-sensitive) port a external interrupts (enable or disable) port pulldown resistors (enable or disable) stop instruction (stop mode or halt mode) crystal oscillator internal resistor (enable or disable) eprom security (enable or disable) short oscillator delay (enable or disable) take the following steps to program the mask option register (mor): 1. apply the programming voltage, v pp , to the irq /v pp pin. 2. write to the mor. 3. set the mpgm bit and wait for a time, t mpgm . 4. clear the mpgm bit. 5. reset the mcu. soscd ? short oscillator delay bit the soscd bit controls the oscillator stabilizati on counter. the normal stabilization delay following reset or exit from stop mode is 4064 t cyc . setting soscd enables a 128 t cyc stabilization delay. 1 = short oscillator delay enabled 0 = short oscillator delay disabled epmsec ? eprom security bit the epmsec bit controls access to the eprom/otprom. 1 = external access to eprom/otprom denied 0 = external access to eprom/otprom not denied oscres ? oscillator internal resistor bit the oscres bit enables a 2-m ? internal resistor in the oscillator circuit. 1 = oscillator internal resistor enabled 0 = oscillator internal resistor disabled note program the oscres bit to logic 0 in devices using low-speed crystal or rc oscillators with external resistor. address: $07f1 bit 7654321bit 0 read: soscd epmsec oscres swait swpdi pirq level copen write: reset: unaffected by reset figure 2-4. mask option register (mor) memory MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 28 freescale semiconductor swait ? stop-to-wait conversion bit the swait bit enables halt mode. when the swait bit is set, the cpu interprets the stop instruction as a wait instruction, and the mcu enters halt mode. halt mode is the same as wait mode, except that an oscillator stabilization delay of 1 to 4064 t cyc occurs after exiting halt mode. 1 = halt mode enabled 0 = halt mode not enabled swpdi ? software pulldown inhibit bit the swpdi bit inhibits software control of the i/o port pulldown devices. the swpdi bit overrides the pulldown inhibit bits in the por t pulldown inhibit registers. 1 = software pulldown control inhibited 0 = software pulldown control not inhibited pirq ? port a external interrupt bit the pirq bit enables the pa0?pa3 pins to function as external interrupt pins. 1 = pa0?pa3 enabled as external interrupt pins 0 = pa0?pa3 not enabled as external interrupt pins level ?external interrupt sensitivity bit the level bit controls external in terrupt triggering sensitivity. 1 = external interrupts triggered by active edges and active levels 0 = external interrupts triggered only by active edges copen ? cop enable bit the copen bit enables the cop watchdog. 1 = cop watchdog enabled 0 = cop watchdog disabled 2.9 eprom programming characteristics table 2-1. eprom programming characteristics (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ?40 c to +85 c characteristic symb ol min typ max unit programming voltage irq /v pp v pp 16.0 16.5 17.0 v programming current irq /v pp i pp ?| 3.0 10.0 ma programming time per array byte mor t epgm t mpgm 4 4 ? ? ? ? ms MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 29 chapter 3 computer operating properly module (cop) 3.1 introduction the computer operating properly (cop) watchdog resets the mcu in case of software failure. software that is operating properly periodically services the cop watchdog and prevents cop reset. the cop watchdog function is programmable by the co pen bit in the mask option register. 3.2 features the computer operating properly module (cop) includes these features: protection from runaway software wait mode and halt mode operations 3.3 operation operation of the cop m odule is discussed here. 3.3.1 cop watchdog timeout four counter stages at the end of the timer make up the cop watchdog. the cop resets the mcu if the timeout period occurs before the cop watchdog timer is cleared by application software and the irq /v pp pin voltage is between v ss and v dd . periodically clearing the counter starts a new timeout period and prevents cop reset. a cop watchdog timeout indicates that the software is not executing instructions in the correct sequence. note the internal clock drives the cop watchdog. therefore, the cop watchdog cannot generate a reset for errors that cause the internal clock to stop. the cop watchdog depends on a power supply voltage at or above a minimum specification and is not guaranteed to protect against brownout. 3.3.2 cop watchdog timeout period the cop watchdog timer function is implemented by divi ding the output of the real-time interrupt circuit (rti) by eight. the rti select bits in the timer status and control register control rti output, and the selected output drives the cop watchdog. (see timer status and control register in chapter 9 multifunction timer module .) note the minimum cop timeout period is seven times the rti period. the cop is cleared asynchronously with the value in the rti divider; hence, the cop timeout period will vary between 7x and 8x the rti period. computer operating properly module (cop) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 30 freescale semiconductor 3.3.3 clearing the cop watchdog to clear the cop watchdog and prevent a cop reset, write a logic 0 to bit 0 (copc) of the cop register at location $07f0 (see figure 3-1 ). clearing the cop bit disables th e cop watchdog timer regardless of the irq /v pp pin voltage. if the main program executes within the cop timeout period, the clearing routine should be executed only once. if the main program takes longer than the co p timeout period, the clearing routine must be executed more than once. note place the clearing routine in the main program and not in an interrupt routine. clearing the cop watchdog in an interrupt routine might prevent cop watchdog timeouts even though the main program is not operating properly. 3.4 interrupts the cop watchdog does not generate interrupts. 3.5 cop register the cop register (copr) is a write-only register that returns the contents of eprom location $07f0 when read. copc ? cop clear bit this write-only bit resets the cop watchdog. reading address $07f0 returns undefined results. 3.6 low-power modes the stop and wait instructions have the following effects on the cop watchdog. 3.6.1 stop mode the stop instruction clears the cop watchdog count er and disables the clock to the cop watchdog. note to prevent the stop instruction from disabling the cop watchdog, program the stop-to-wait conversion bit (swait) in the mask option register to logic 1. address: $07f0 bit 7654321bit 0 read: write: copc reset:uuuuuuu0 = unimplemented u = unaffected figure 3-1. cop register (copr) low-power modes MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 31 upon exit from stop mode by external reset: the counter begins counting from $0000. the counter is cleared again after the oscillator stabilization delay and begins counting from $0000 again. upon exit from stop mode by external interrupt: the counter begins counting from $0000. the counter is not cleared again after the oscillator st abilization delay and continues counting throughout the oscillator stabilization delay. note immediately after exiting stop mode by external interrupt, service the cop to ensure a full cop timeout period. 3.6.2 wait mode the wait instruction has no effect on the cop watchdog. note to prevent a cop timeout during wait mode, exit wait mode periodically to service the cop. computer operating properly module (cop) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 32 freescale semiconductor MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 33 chapter 4 central processor unit (cpu) 4.1 introduction the central processor unit (cpu) consists of a cpu co ntrol unit, an arithmetic/logic unit (alu), and five cpu registers. the cpu control unit fetches an d decodes instructions. the alu executes the instructions. the cpu registers contain data, addresses, and status bits that reflect the results of cpu operations. 4.2 features features of the cpu include: 4.0-mhz bus frequency on standard part 8-bit accumulator 8-bit index register 11-bit program counter 6-bit stack pointer condition code register with five status flags 62 instructions 8 addressing modes power-saving stop, wait, halt, and data-retention modes the programming model is shown in figure 4-1 . 4.3 cpu control unit the cpu control unit fetches and decodes instructions during program operation. the control unit selects the memory locations to read and write and coordinates the timing of all cpu operations. 4.4 arithmetic/logic unit the arithmetic/logic unit (alu) performs the arithm etic, logic, and manipulat ion operations decoded from the instruction set by the cpu control unit. the alu produces the results called for by the program and sets or clears status and control bits in the condition code register (ccr). central processor unit (cpu) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 34 freescale semiconductor figure 4-1. programming model accumulator (a) index register (x) condition code register (ccr) program counter (pc) stack pointer (sp) half-carry flag interrupt mask negative flag zero flag carry/borrow flag 0 4 75 6 321 0 arithmetic/logic unit cpu control unit 0 4 75 6 321 0 4 75 6 321 8 12 15 13 14 11 10 9 000000011 0 00 0 4 75 6 321 8 12 15 13 14 11 10 9 111hinzc 0 4 75 6 321 0 0 cpu registers MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 35 4.5 cpu registers the m68hc05 cpu contains five registers that control and monitor mcu operation: accumulator index register stack pointer program counter condition code register cpu registers are not memory mapped. 4.5.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and results of alu operations. 4.5.2 index register in the indexed addressing modes, the cpu uses the by te in the index register to determine the conditional address of the operand. the index register also can serve as a temporary storage location or a counter. 4.5.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset or after the reset stack pointer instruction (rsp), the stack pointer is preset to $00ff. the address in the stack pointer decrements after a byte is stacked and increments before a byte is unstacked. bit 7654321bit 0 read: write: reset: unaffected by reset figure 4-2. accumulator (a) bit 7654321bit 0 read: write: reset: unaffected by reset figure 4-3. index register (x) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read:0000000011 write: reset:0000000011111111 = unimplemented figure 4-4. stack pointer (sp) central processor unit (cpu) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 36 freescale semiconductor the 10 most significant bits of the stack pointer are permanently fixed at 0000000011, so the stack pointer produces addresses from $00c0 to $00ff. if subrouti nes and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00ff and begi ns writing over the prev iously stored data. a subroutine uses two stack locations; an interrupt uses five locations. 4.5.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. the five most significant bits of th e program counter are ignored and appear as 00000. normally, the address in the program counter automat ically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 4.5.5 condition code register the condition code register is an 8- bit register whose three most signif icant bits are permanently fixed at 111. the condition code register contains the interrupt mask and four flags that indicate the results of the instruction just executed. h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an add or adc operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. i ? interrupt mask setting the interrupt mask disables interrupts. if an interrupt request occurs whil e the interrupt mask is logic 0, the cpu saves the cpu registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. if an interrupt request occurs while the interrupt mask is logic 1, the interrupt request is latched. normally, the cpu processes the latched interrupt request as soon as the interrupt mask is cleared again. a return from interrupt instruction (rti) unstacks the cpu registers, restoring the interrupt mask to its cleared state. after any reset, the interrupt mask is set and can be cleared only by a software instruction. n ? negative flag the cpu sets the negative flag when an alu operation produces a negative result. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 reset: 0 0 0 0 0 loaded with vector from $07fe and $07ff figure 4-5. program counter (pc) bit 7654321bit 0 read: 1 1 1 hinzc write: reset:111u1uuu = unimplemented u = unaffected figure 4-6. condition code register (ccr) instruction set MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 37 z ? zero flag the cpu sets the zero flag when an alu operation produces a result of $00. c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some logical operations and data manipulation instructions also clear or set the carry/borrow flag. 4.6 instruction set the mcu instruction set has 62 instructions and uses eight addressing modes. 4.6.1 addressing modes the cpu uses eight addressing modes for flexibility in accessing data. the addressing modes provide eight different ways for the cpu to find the data r equired to execute an instruction. the eight addressing modes are: inherent immediate direct extended indexed, no offset indexed, 8-bit offset indexed, 16-bit offset relative 4.6.1.1 inherent inherent instructions are those that have no operand, such as return-from-interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry flag (sec) and increment accumulator (inca). inherent instructions require no operand address and are one byte long. 4.6.1.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instruct ions require no operand addres s and are two bytes long. the opcode is the first byte, and the i mmediate data value is the second byte. 4.6.1.3 direct direct instructions can access any of the first 256 me mory locations with two byte s. the first byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. 4.6.1.4 extended extended instructions use three bytes and can access any address in memory. the first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. central processor unit (cpu) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 38 freescale semiconductor when using the freescale assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. 4.6.1.5 indexed, no offset indexed instructions with no offset are 1-byte inst ructions that can access data with variable addresses within the first 256 memory locations. the index register contains the low byte of the effective address of the operand. the cpu automatically uses $00 as t he high byte, so these instructions can address locations $0000?$00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or input/output (i/o) location. 4.6.1.6 indexed, 8-bit offset indexed, 8-bit offset instructions are 2-byte instru ctions that can access data with variable addresses within the first 511 memo ry locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the e ffective address of the operand. these instructions can access locations $0000?$01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory lo cations and could extend as far as location 510 ($01fe). the k value is typically in the index regist er, and the address of the beginning of the table is in the byte following the opcode. 4.6.1.7 indexed, 16-bit offset indexed, 16-bit offset instructions are 3-byte instruct ions that can access data with variable addresses at any location in memory. the cpu adds the unsigned by te in the index register to the two unsigned bytes following the opcode. the sum is the effective addres s of the operand. the first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. indexed, 16-bit offset instructions are useful for se lecting the kth element in an n-element table anywhere in memory. as with direct and extended address ing, the freescale assembler determines the shortest form of indexed addressing. 4.6.1.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, two?s complement byte that gives a branching range of ?128 to +127 bytes from the address of the next location after the branch instruction. when using the freescale assembler, the programmer does not need to calculate the offset because the assembler determines the proper offset and verifies that it is within the span of the branch. instruction set MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 39 4.6.2 instruction types the mcu instructions fall into the following five categories: register/memory instructions read-modify-write instructions jump/branch instructions bit manipulation instructions control instructions 4.6.2.1 register/memory instructions these instructions operate on cpu registers and memo ry locations. most of them use two operands. one operand is in either the accumulator or the index r egister. the cpu finds the other operand in memory. table 4-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub central processor unit (cpu) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 40 freescale semiconductor 4.6.2.2 read-modify-write instructions these instructions read a memory location or a regist er, modify its contents, and write the modified value back to the memory location or to the register. note do not use read-modify-write instructi ons on registers with write-only bits. 4.6.2.3 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump-to-subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. the brclr and brset instructions cause a branch bas ed on the state of any readable bit in the first 256 memory locations. these 3-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be test ed is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from ?128 to +127 from the address of the next location after the table 4-2. read-modify-write instructions instruction mnemonic arithmetic shift left (same as lsl) asl arithmetic shift right asr bit clear bclr (1) 1. unlike other read-modify-write instructions, bclr and bset use only direct addressing. bit set bset (1) clear register clr complement (one?s complement) com decrement dec increment inc logical shift left (same as asl) lsl logical shift right lsr negate (two?s complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst (2) 2. tst is an exception to the read-modify-write sequence because it does not write a replacement value. instruction set MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 41 branch instruction. the cpu also transfers the test ed bit to the carry/borrow bit of the condition code register. note do not use brclr or brset instructions on registers with write-only bits. table 4-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr central processor unit (cpu) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 42 freescale semiconductor 4.6.2.4 bit manipulation instructions the cpu can set or clear any writable bit in the fi rst 256 bytes of memory, which includes i/o registers and on-chip ram locations. the cpu can also test and branch based on the state of any bit in any of the first 256 memory locations. note do not use bit manipulation instructi ons on registers with write-only bits. 4.6.2.5 control instructions these instructions act on cpu registers and control cpu operation during program execution. table 4-4. bit manipulation instructions instruction mnemonic bit clear bclr branch if bit clear brclr branch if bit set brset bit set bset table 4-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait instruction set MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 43 4.6.3 instruction set summary table 4-6. instruction se t summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a (a) (m) ? ? ? imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) ? ? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right ? ? dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? c = 0 ????? rel 24 rr 3 bclr n opr clear bit n mn 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? c = 1 ????? rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? z = 1 ????? rel 27 rr 3 bhcc rel branch if half-carry bit clear pc (pc) + 2 + rel ? h = 0 ????? rel 28 rr 3 bhcs rel branch if half-carry bit set pc (pc) + 2 + rel ? h = 1 ????? rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? c z = 0 ????? rel 22 rr 3 bhs rel branch if higher or same pc (pc) + 2 + rel ? c = 0 ????? rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ????? rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ????? rel 2e rr 3 c b0 b7 0 b0 b7 c central processor unit (cpu) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 44 freescale semiconductor bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) ? ? ? imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? c = 1 ????? rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? c z = 1 ????? rel 23 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? i = 0 ????? rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? n = 1 ????? rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? i = 1 ????? rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? z = 0 ????? rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? n = 0 ????? rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ? 1 = 1 ????? rel 20 rr 3 brclr n opr rel branch if bit n clear pc (pc) + 2 + rel ? mn = 0 ???? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 + rel ? 1 = 0 ????? rel 21 rr 3 brset n opr rel branch if bit n set pc (pc) + 2 + rel ? mn = 1 ???? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n opr set bit n mn 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ????? rel ad rr 6 clc clear carry bit c 0 ???? 0 inh 98 2 cli clear interrupt mask i 0 ? 0 ??? inh 9a 2 table 4-6. instruction se t summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc instruction set MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 45 clr opr clra clrx clr opr ,x clr ,x clear byte m $00 a $00 x $00 m $00 m $00 ?? 0 1 ? dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) ? (m) ? ? imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (a) x (x ) = $ff ? (x) m (m ) = $ff ? (m) m (m ) = $ff ? (m) ?? 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) ? (m) ? ? imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a (a) (m) ? ? ? imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr ,x inc ,x increment byte m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc jump address ????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n (n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc effective address ????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 table 4-6. instruction se t summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc central processor unit (cpu) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 46 freescale semiconductor lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a (m) ? ? ? imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x (m) ? ? ? imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) ? ? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right ? ? 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a (x) (a) 0 ??? 0 inh 42 1 1 neg opr nega negx neg opr ,x neg ,x negate byte (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ?? dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation ????? inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a (a) (m) ? ? ? imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit ? ? dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit ? ? dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp $00ff ? ???? inh 9c 2 table 4-6. instruction se t summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 0 b0 b7 c 0 c b0 b7 b0 b7 c instruction set MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 47 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 9 rts return from subroutine sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ????? inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a (a) ? (m) ? (c) ? ? imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c 1 ???? 1 inh 99 2 sei set interrupt mask i 1 ? 1 ??? inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m (a) ? ? ? dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin ? 0 ? ? ? inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m (x) ? ? ? dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a (a) ? (m) ? ? imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ? 1 ??? inh 83 1 0 tax transfer accumulator to index register x (a) ????? inh 97 2 tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) ? $00 ? ? ? dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 table 4-6. instruction se t summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc central processor unit (cpu) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 48 freescale semiconductor 4.7 opcode map see table 4-7 . txa transfer index register to accumulator a (x) ????? inh 9f 2 wait stop cpu clock and enable interrupts ? 0 ? ? ? inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flag pc program counter ccr condition code register pch p rogram counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit o ffset addressing rr relative pr ogram counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry flag z zero flag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix1 indexed, 8-bit offset addressing mode loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative flag set or cleared n any bit ? not affected table 4-6. instruction se t summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 49 opcode map table 4-7. opcode map bit manipulation branch read-modif y-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789abcdef 0 5 brset0 3dir 5 bset0 2dir 3 bra 2rel 5 neg 2dir 3 nega 1inh 3 negx 1inh 6 neg 2ix1 5 neg 1ix 9 rti 1inh 2 sub 2imm 3 sub 2dir 4 sub 3 ext 5 sub 3ix2 4 sub 2ix1 3 sub 1ix 0 1 5 brclr0 3dir 5 bclr0 2dir 3 brn 2rel 6 rts 1inh 2 cmp 2imm 3 cmp 2dir 4 cmp 3 ext 5 cmp 3ix2 4 cmp 2ix1 3 cmp 1ix 1 2 5 brset1 3dir 5 bset1 2dir 3 bhi 2rel 11 mul 1inh 2 sbc 2imm 3 sbc 2dir 4 sbc 3 ext 5 sbc 3ix2 4 sbc 2ix1 3 sbc 1ix 2 3 5 brclr1 3dir 5 bclr1 2dir 3 bls 2rel 5 com 2dir 3 coma 1inh 3 comx 1inh 6 com 2ix1 5 com 1ix 10 swi 1inh 2 cpx 2imm 3 cpx 2dir 4 cpx 3 ext 5 cpx 3ix2 4 cpx 2ix1 3 cpx 1ix 3 4 5 brset2 3dir 5 bset2 2dir 3 bcc 2rel 5 lsr 2dir 3 lsra 1inh 3 lsrx 1inh 6 lsr 2ix1 5 lsr 1ix 2 and 2imm 3 and 2dir 4 and 3 ext 5 and 3ix2 4 and 2ix1 3 and 1ix 4 5 5 brclr2 3dir 5 bclr2 2dir 3 bcs/blo 2rel 2 bit 2imm 3 bit 2dir 4 bit 3 ext 5 bit 3ix2 4 bit 2ix1 3 bit 1ix 5 6 5 brset3 3dir 5 bset3 2dir 3 bne 2rel 5 ror 2dir 3 rora 1inh 3 rorx 1inh 6 ror 2ix1 5 ror 1ix 2 lda 2imm 3 lda 2dir 4 lda 3 ext 5 lda 3ix2 4 lda 2ix1 3 lda 1ix 6 7 5 brclr3 3dir 5 bclr3 2dir 3 beq 2rel 5 asr 2dir 3 asra 1inh 3 asrx 1inh 6 asr 2ix1 5 asr 1ix 2 ta x 1inh 4 sta 2dir 5 sta 3 ext 6 sta 3ix2 5 sta 2ix1 4 sta 1ix 7 8 5 brset4 3dir 5 bset4 2dir 3 bhcc 2rel 5 asl/lsl 2dir 3 asla/lsla 1inh 3 aslx/lslx 1inh 6 asl/lsl 2ix1 5 asl/lsl 1ix 2 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3 ext 5 eor 3ix2 4 eor 2ix1 3 eor 1ix 8 9 5 brclr4 3dir 5 bclr4 2dir 3 bhcs 2rel 5 rol 2dir 3 rola 1inh 3 rolx 1inh 6 rol 2ix1 5 rol 1ix 2 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3 ext 5 adc 3ix2 4 adc 2ix1 3 adc 1ix 9 a 5 brset5 3dir 5 bset5 2dir 3 bpl 2rel 5 dec 2dir 3 deca 1inh 3 decx 1inh 6 dec 2ix1 5 dec 1ix 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3 ext 5 ora 3ix2 4 ora 2ix1 3 ora 1ix a b 5 brclr5 3dir 5 bclr5 2dir 3 bmi 2rel 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3 ext 5 add 3ix2 4 add 2ix1 3 add 1ix b c 5 brset6 3dir 5 bset6 2dir 3 bmc 2rel 5 inc 2dir 3 inca 1inh 3 incx 1inh 6 inc 2ix1 5 inc 1ix 2 rsp 1inh 2 jmp 2dir 3 jmp 3 ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix c d 5 brclr6 3dir 5 bclr6 2dir 3 bms 2rel 4 tst 2dir 3 tsta 1inh 3 tstx 1inh 5 tst 2ix1 4 tst 1ix 2 nop 1inh 6 bsr 2rel 5 jsr 2dir 6 jsr 3 ext 7 jsr 3ix2 6 jsr 2ix1 5 jsr 1ix d e 5 brset7 3dir 5 bset7 2dir 3 bil 2rel 2 stop 1inh 2 ldx 2imm 3 ldx 2dir 4 ldx 3 ext 5 ldx 3ix2 4 ldx 2ix1 3 ldx 1ix e f 5 brclr7 3dir 5 bclr7 2dir 3 bih 2rel 5 clr 2dir 3 clra 1inh 3 clrx 1inh 6 clr 2ix1 5 clr 1ix 2 wait 1inh 2 txa 1inh 4 stx 2dir 5 stx 3 ext 6 stx 3ix2 5 stx 2ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 50 freescale semiconductor central processor unit (cpu) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 51 chapter 5 external interrupt module (irq) 5.1 introduction the external interrupt (irq) module provides asynchr onous external interrupts to the cpu. the following sources can generate external interrupts: irq /v pp pin pa0?pa3 pins 5.2 features the external interrupt module (irq) includes these features: dedicated external interrupt pin (irq /v pp ) selectable interrupt on four input/output (i/o) pins (pa0?pa3) programmable edge-only or edge- and level-interrupt sensitivity 5.3 operation the interrupt request/programming voltage pin (irq /v pp ) and port a pins 0?3 (pa0?pa3) provide external interrupts. the pirq bit in the mask option register (mor) enables pa0?pa3 as irq interrupt sources, which are combined into a single or?ing function to be latched by the irq latch. figure 5-1 shows the structure of the irq module. after completing its current instruction, the cpu tests the irq latch. if the irq latch is set, the cpu then tests the i bit in the condition code register and the irqe bit in the irq status and control register. if the i bit is clear and the irqe bit is set, the cpu then begi ns the interrupt sequence. this interrupt is serviced by the interrupt service routine located at $07fa and $07fb. the cpu clears the irq latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. as soon as the i bit is cleared during the return from interrupt, the cpu can recognize the new interrupt request. figure 5-3 shows the sequence of events caused by an interrupt. 5.3.1 irq /v pp pin an interrupt signal on the irq /v pp pin latches an external interrupt re quest. the level bit in the mask option register provides negative edge-sensitiv e triggering or both negative edge-sensitive and low level-sensitive triggering for the interrupt function. if edge- and level-sensitive triggering is selected, a falling edge or a low level on the irq /v pp pin latches an external interrupt request. edge- and level-sensit ive triggering allows the use of multiple wired-or external interrupt sources. an external interrupt request is latched as long as any source is holding the irq /v pp pin low. if level-sensitive triggering is selected, the irq /v pp input requires an external resistor to v dd for wired-or operation. if the irq /v pp pin is not used, it must be tied to the v dd supply. external interrupt module (irq) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 52 freescale semiconductor figure 5-1. irq module block diagram if edge-sensitive-only triggering is selected, a falling edge on the irq /v pp pin latches an external interrupt request. a subsequent external interrupt request can be latched only after the voltage level on the irq /v pp pin returns to logic 1 and then falls again to logic 0. the irq /v pp pin contains an internal schmitt trigger as pa rt of its input to impr ove noise immunity. the voltage on this pin can affect the m ode of operation and should not exceed v dd . 5.3.2 optional external interrupts the inputs for the lower four bits of port a (pa0?pa3) can be connected to the irq pin input of the cpu if enabled by the pirq bit in the mask option regist er. this capability allows keyboard scan applications where the transitions or levels on the i/o pins will behave the same as the irq /v pp pin except for the inverted phase (logic 1, rising edge). the active state of the irq /v pp pin is a logic 0 (falling edge). the pa0?pa3 pins are selected as a group to function as irq interrupts and are enabled by the irqe bit in the irq status and control register. the pa0? pa3 pins can be positiv e-edge triggered only or positive-edge and high-level triggered. addr. register name bit 7 6 5 4 3 2 1 bit 0 $000a irq status and control register (iscr) see page 54. read: irqe 000irqf000 write: r irqr reset:10000000 = unimplemented r = reserved figure 5-2. irq module i/o register summary pirq level-sensitive trigger pa3 pa2 pa1 irq pa0 v dd (mor level bit) reset irq vector fetch external interrupt request (mor) to bih & bil instruction processing irqf irqr irqe dq ck irq clr latch operation MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 53 figure 5-3. interrupt flowchart external interrupt? i bit set? timer interrupt? fetch next instruction. swi instruction? rti instruction? stack pcl, pch, x, a, ccr. set i bit. load pc with interrupt vector. yes yes yes yes yes unstack ccr, a, x, pch, pcl. execute instruction. clear irq latch. no no no no no from reset external interrupt module (irq) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 54 freescale semiconductor if edge- and level-sensitive triggering is selected, a rising edge or a high level on a pa0?pa3 pin latches an external interrupt request. edge- and level-sensitive triggering allows the use of multiple wired-or external interrupt sources. as long as any source is holding a pa0?pa3 pin high, an external interrupt request is latched, and the cpu continues to execute the interrupt service routine. if edge-sensitive only triggering is selected, a rising edge on a pa0?pa3 pin latches an external interrupt request. a subsequent external interrupt request can be latched only after the voltage level of the previous interrupt signal returns to logi c 0 and then rises again to logic 1. note the bih and bil instructions apply only to the level on the irq /v pp pin itself and not to the output of the logic or function with the pa0 ? pa3 pins. the state of the individual port a pins can be checked by reading the appropriate port a pins as inputs. enabled pa0 ? pa3 pins cause an irq interrupt regardless of whether these pins are configured as inputs or outputs. the irq pin has an internal schmitt trigger. the optional external interrupts (pa0 ? pa3) do not have internal schmitt triggers. the interrupt mask bit (i) in the condition code register (ccr) disables all maskable interrupt requests, including external interrupt requests. 5.4 irq status and control register the irq status and control register (iscr) controls and monitors operation of th e irq module. all unused bits in the iscr read as logic 0s. the irqf bit is cleared and the irqe bit is set by reset. irqr ? interrupt request reset bit this write-only bit clears the ex ternal interrupt request flag. 1 = clears external interrupt and irqf bit 0 = no effect on external interrupt and irqf bit irqf ? external interrupt request flag the external interrupt request flag is a clearable, read-only bit that is set when an external interrupt request is pending. reset clears the irqf bit. 1 = external interrupt request pending 0 = no external interrupt request pending irqe ? external interrupt request enable bit this read/write bit enables external interrupts. reset sets the irqe bit. 1 = external interrupt requests enabled 0 = external interrupt requests disabled address: $000a bit 7654321bit 0 read: irqe 000irqf000 write: r irqr reset:10000000 = unimplemented r = reserved figure 5-4. irq status and control register (iscr) timing MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 55 the stop and wait instructions set the irqe bit so that an external interrupt can bring the mcu out of these low-power modes. in addition, reset sets the i bit which masks all interrupt sources. 5.5 timing figure 5-5. external interrupt timing table 5-1. external interrupt timing (v dd = 5.0 vdc) (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ?40 c to + 85 c, unless otherwise noted. characteristic symbol min max unit irq interrupt pulse width low (edge-triggered) t ilih 1.5 ? t cyc (2) 2. t cyc = 1/f op ; f op = f osc /2. irq interrupt pulse width (edge- and level-triggered) t ilih 1.5 note (3) 3. the minimum t ilil should not be less than the number of interrupt se rvice routine cycles plus 19 t cyc . t cyc pa0?pa3 interrupt pulse width high (edge-triggered) t ilil 1.5 ? t cyc pa0?pa3 interrupt pulse width high (edge- and level-triggered) t ilih 1.5 note (3) t cyc table 5-2. external interrupt timing (v dd = 3.3 vdc) (1) 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = ?40 c to + 85 c, unless otherwise noted. characteristic symbol min max unit irq interrupt pulse width low (edge-triggered) t ilih 1.5 ? t cyc (2) 2. t cyc = 1/f op ; f op = f osc /2. irq interrupt pulse width (edge- and level-triggered) t ilih 1.5 note (3) 3. the minimum t ilil should not be less than the number of interrupt se rvice routine cycles plus 19 t cyc . t cyc pa0?pa3 interrupt pulse width high (edge-triggered) t ilil 1.5 ? t cyc pa0?pa3 interrupt pulse width high (edge- and level-triggered) t ilih 1.5 note (3) t cyc irq (internal) t ilih t ilil t ilih irq /v pp pin irq 1 irq n . . . external interrupt module (irq) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 56 freescale semiconductor MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 57 chapter 6 low-power modes 6.1 introduction the mcu can enter the following low-power standby modes: stop mode ? the stop instruction puts the mcu in its lowest power-consumption mode. wait mode ? the wait instruction puts the mcu in an intermediate power-consumption mode. halt mode ? halt mode is identical to wait mode, except that an oscillator stabilization delay of 1 to 4064 internal clock cycles occurs when the mcu exits halt mode. the stop-to-wait conversion bit, swait, in the mask option register, enables halt mode. enabling halt mode prevents the computer operating properly (cop) watchdog from being inadvertently turned off by a stop instruction. data-retention mode ? in data-retention mode, the mcu retains ram contents and cpu register contents at v dd voltages as low as 2.0 vdc. the data-retention feature allows the mcu to remain in a low power-consumption state during which it retains data, but the cpu cannot execute instructions. 6.2 exiting stop and wait modes the following events bring the mcu out of stop mode and load the program counter with the reset vector or with an interrupt vector: exiting stop mode external reset ? a logic 0 on the reset pin resets the mcu, starts the cpu clock, and loads the program counter with the contents of locations $07fe and $07ff. external interrupt ? a high-to-low transition on the irq /v pp pin or a low-to-high transition on an enabled port a external interrupt pin starts the cpu clock and loads the program counter with the contents of locations $07fa and $07fb. exiting wait mode external reset ? a logic 0 on the reset pin resets the mcu, starts the cpu clock, and loads the program counter with the contents of locations $07fe and $07ff. external interrupt ? a high-to-low transition on the irq /v pp pin or a low-to-high transition on an enabled port a external interrupt pin starts the cpu clock and loads the program counter with the contents of locations $07fa and $07fb. cop watchdog reset ? a timeout of the cop watchdog resets the mcu, starts the cpu clock, and loads the program counter with the contents of locations $07fe and $07ff. software can enable timer interrupts so that the mcu periodically can exit wait mode to reset the cop watchdog. timer interrupt ? real-time interrupt requests and timer overflow interrupt requests start the mcu clock and load the program counter with the contents of locations $07f8 and $07f9. low-power modes MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 58 freescale semiconductor 6.3 effects of stop and wait modes the stop and wait instructions have the following effects on mcu modules. 6.3.1 clock generation effects of stop and wait on clock generation are discussed here. 6.3.1.1 stop the stop instruction disables the internal oscillator, stopping the cp u clock and all peripheral clocks. after exiting stop mode, the cpu clock and all enabled pe ripheral clocks begin running after the oscillator stabilization delay. note the oscillator stabilization delay hold s the mcu in reset for the first 4064 internal clock cycles. 6.3.1.2 wait the wait instruction disables the cpu clock. after exiting wait mode, the cpu clock and all ena bled peripheral clocks immediately begin running. 6.3.2 cpu effects of stop and wait on the cpu are discussed here. 6.3.2.1 stop the stop instruction: clears the interrupt mask (i bit) in the c ondition code register, enabling external interrupts disables the cpu clock after exiting stop mode, the cpu clock begins ru nning after the oscillator stabilization delay. after exit from stop mode by external interrupt, the i bit remains clear. after exit from stop mode by reset, the i bit is set. 6.3.2.2 wait the wait instruction: clears the interrupt mask (i bit) in t he condition code register, enabling interrupts disables the cpu clock after exit from wait mode by interrupt, the i bit remains clear. after exit from wait mode by reset, the i bit is set. 6.3.3 cop watchdog effects of stop and wait on the cop watchdog are discussed here. effects of stop and wait modes MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 59 6.3.3.1 stop the stop instruction: clears the cop watchdog counter disables the cop watchdog clock note to prevent the stop instruction from disabling the cop watchdog, program the stop-to-wait conversion bit (swait) in the mask option register to logic 1. after exit from stop mode by external interrup t, the cop watchdog counter immediately begins counting from $0000 and continues counting thro ughout the oscillator stabilization delay. note immediately after exiting stop mode by external interrupt, service the cop to ensure a full cop timeout period. after exit from stop mode by reset: the cop watchdog counter immediat ely begins counting from $0000. the cop watchdog counter is cleared at the end of the oscillator stabilization delay and begins counting from $0000 again. 6.3.3.2 wait the wait instruction has no effect on the cop watchdog. note to prevent a cop timeout during wait mode, exit wait mode periodically to service the cop. 6.3.4 timer effects of stop and wait on the timer are discussed here. 6.3.4.1 stop the stop instruction: clears the rtie, tofe, rtif, and tof bits in the timer status and control register, disabling timer interrupt requests and removing any pending timer interrupt requests disables the clock to the timer after exiting stop mode by external interrupt, the time r immediately resumes counting from the last value before the stop instruction and continues countin g throughout the oscillator stabilization delay. after exiting stop mode by reset and after the oscillator stabilization delay, the timer resumes operation from its reset state. 6.3.4.2 wait the wait instruction has no effect on the timer. 6.3.5 eprom/otprom effects of stop and wait on the eprom/otprom are discussed here. low-power modes MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 60 freescale semiconductor 6.3.5.1 stop the stop instruction during eprom programming cl ears the epgm bit in the eprom programming register, removing the program ming voltage from the eprom. 6.3.5.2 wait the wait instruction has no effect on eprom/otprom operation. 6.4 data-retention mode in data-retention mode, the mcu retains ra m contents and cpu register contents at v dd voltages as low as 2.0 vdc. the data-retention feature allows the mcu to remain in a low power-consumption state during which it retains data, but the cpu cannot execute instructions. to put the mcu in data-retention mode: 1. drive the reset pin to logic 0. 2. lower the v dd voltage. the reset pin must remain low continuously during data-retention mode. to take the mcu out of data-retention mode: 1. return v dd to normal operating voltage. 2. return the reset pin to logic 1. 6.5 timing figure 6-1. stop mode recovery timing t ilih oscillator stabilization delay (5) osc t rl reset irq /v pp irq /v pp internal clock internal address notes: 1. internal clocking from osc1 pin 2. edge-triggered external interrupt mask option 3. edge- and level-triggered external interrupt mask option 4. reset vector shown as example reset or interrupt vector fetch $07fe $07fe $07fe $07fe $07fe $07ff (note 4) bus (note 3) (note 2) (note 1) 5. 4064 cycles or 128 cycles, depending on state of soscd bit in mor timing MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 61 figure 6-2. stop/halt/wait flowchart stop swait bit set? clear i bit in ccr. set irqe bit in iscr. clear tof, rtif, toie, and rtie bits in tscr. turn off internal oscillator. external reset? external interrupt? no no no turn on internal oscillator. reset stabilization timer. yes yes halt yes end of stabilization delay? yes no yes no no no cop reset? timer interrupt? external interrupt? external reset? clear i bit in ccr. set irqe bit in iscr. turn off cpu clock. timer clock active. yes yes yes yes no no no clear i bit in ccr. set irqe bit in iscr. turn off cpu clock. timer clock active. yes yes yes no no turn on cpu clock. 1. load pc with reset vector or 2. service interrupt. a. save cpu registers on stack. b. set i bit in ccr. c. load pc with interrupt vector. external reset? wait external interrupt? timer interrupt? cop reset? low-power modes MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 62 freescale semiconductor MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 63 chapter 7 parallel i/o ports (ports) 7.1 introduction ten bidirectional pins form one 8-bit input/output (i/o ) port and one 2-bit i/o port. all the bidirectional port pins are programmable as inputs or outputs. note connect any unused i/o pins to an appropriate logic level, either v dd or v ss. although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. addr.register name: bit 7654321bit 0 $0000 port a data register (por- ta) see page 64. read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset $0001 port b data register (portb) see page 66. read: 0 0 see note pb3 pb2 see note write: reset: unaffected by reset $0004 data direction register a (ddra) see page 64. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 67. read: 0 0 see note ddrb3 ddrb2 see note write: reset:00000000 $0010 port a pulldown register (pdra) see page 65. read: write: pdia7 pdia6 pdia5 pdia4 pdia3 pdia2 pdia1 pdia0 reset:00000000 $0011 port b pulldown register (pdrb) see page 68. read: write: see note pdib3 pdib2 see note reset: 000000 = unimplemented note: pb5, pb4, pb1, and pb0 should be configured as inputs at al l times. these bits are available for read/write but are not available externally. configuring them as inputs will ensure that the pulldown devices are enabled, thus properly termi- nating them. figure 7-1. parallel i/o port register summary parallel i/o ports (ports) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 64 freescale semiconductor 7.2 port a port a is an 8-bit bidirectional port. 7.2.1 port a data register the port a data register contains a latch for each port a pin. pa[7:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction regi ster a. reset has no effect on port a data. 7.2.2 data dir ection register a data direction register a determines whether each port a pin is an input or an output. ddra[7:0] ? data direction register a bits these read/write bits contro l port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note avoid glitches on port a pins by writin g to the port a data register before changing data direction regist er a bits from 0 to 1. figure 7-4 shows the i/o logic of port a. address: $0000 bit 7654321bit 0 read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset figure 7-2. port a data register (porta) address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 7-3. data direction register a (ddra) port a MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 65 figure 7-4. port a i/o circuitry writing a logic 1 to a ddra bit enables the output buf fer for the corresponding port a pin; a logic 0 disables the output buffer. when bit ddrax is a logic 1, read ing address $0000 reads the pax data latch. when bit ddrax is a logic 0, reading address $0000 reads the voltage level on th e pin. the data latch can always be written, regardless of the state of its data direction bit. table 7-1 summarizes the operation of the port a pins. 7.2.3 pulldown register a pulldown register a inhibits the pulldown de vices on port a pins programmed as inputs. note if the swpdi bit in the mask option regi ster is programmed to logic 1, reset initializes all port a pins as in puts with disabled pulldown devices. pdia[7:0] ? pulldown inhibit a bits pdia[7:0] disable the port a pulldown devices. reset clears pdia[7:0]. 1 = corresponding port a pulldown device disabled 0 = corresponding port a pulldown device not disabled table 7-1. port a pin operation data direction bit i/o pin mode accesses to data bit read write 0 input, high-impedance pin latch (1) 1. writing affects the data regist er but does not affect input. 1 output latch latch address: $0010 bit 7654321bit 0 read: write: pdia7 pdia6 pdia5 pdia4 pdia3 pdia2 pdia1 pdia0 reset:00000000 = unimplemented figure 7-5. pulldown register a (pdra) read ddra write ddra reset write porta read porta pax internal data bus ddrax pax pdrax swpdi 100- a pulldown (pa0?pa3 to irq module) write pdra 10-ma sink capability (pi ns pa4?pa7 only) parallel i/o ports (ports) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 66 freescale semiconductor 7.2.4 port led drive capability all outputs can drive light-emitting diodes (leds). these pins can sink approximately 10 ma of current to v ss . 7.2.5 port a i/o pin interrupts if the pirq bit in the mask option register is program med to logic 1, pa0?pa3 pins function as external interrupt pins. (see chapter 5 external interrupt module (irq) .) 7.3 port b port b is a 2-bit bidirectional port. 7.3.1 port b data register the port b data register contains a latch for each port b pin. pb[3:2] ? port b data bits these read/write bits are software programmable. data direction of each port b pin is under the control of the corresponding bit in data direction regi ster b. reset has no effect on port b data. note pb4?pb5 and pb0?pb1 should be configured as inputs at all times. these bits are available for read/write but ar e not available externally. configuring them as inputs will ensure that th e pulldown devices are enabled, thus properly terminating them. address: $0001 bit 7654321bit 0 read: 0 0 see note pb3 pb2 see note write: reset: unaffected by reset = unimplemented note: pb5, pb4, pb1, and pb0 should be configured as inputs at all times. these bits are avail- able for read/write but are not available exter nally. configuring them as inputs will ensure that the pulldown devices are enabled, thus properly terminating them. figure 7-6. port b data register (portb) port b MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 67 7.3.2 data dir ection register b data direction register b determines whether each port b pin is an input or an output. ddrb[3:2] ? data direction register b bits these read/write bits contro l port b data direction. reset clears ddrb[3:2], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note avoid glitches on port b pins by writin g to the port b data register before changing data direction regist er b bits from 0 to 1. figure 7-8 shows the i/o logic of port b. figure 7-8. port b i/o circuitry writing a logic 1 to a ddrb bit enables the output buf fer for the corresponding port b pin; a logic 0 disables the output buffer. when bit ddrbx is a logic 1, reading address $0001 reads the pbx data latch. when bit ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 7-2 summarizes the operation of the port b pins. address: $0005 bit 7654321bit 0 read: 0 0 see notes ddrb3 ddrb2 see note write: reset:00000000 = unimplemented note: ddrb5, ddrb4, ddrb1, and ddrb0 should be c onfigured as inputs at all times. these bits are available for read/write but are not av ailable externally. configuring them as inputs will ensure that the pulldown devices ar e enabled, thus properly terminating them. figure 7-7. data direction register b (ddrb) read ddrb write ddrb reset write portb read portb pbx internal data bus ddrbx pbx pdrbx swpdi 100- a pulldown write pdrb parallel i/o ports (ports) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 68 freescale semiconductor 7.3.3 pulldown register b pulldown register b inhibits the pulldown de vices on port b pins programmed as inputs. note if the swpdi bit in the mask option regi ster is programmed to logic 1, reset initializes all port b pins as in puts with disabled pulldown devices. pdib[3:2] ? pulldown inhibit b bits pdib[3:2] disable the port b pulldown devices. reset clears pdib[3:2]. 1 = corresponding port b pulldown device disabled 0 = corresponding port b pulldown device not disabled table 7-2. port b pin operation data direction bit i/o pin mode accesses to data bit read write 0 input, high-impedance pin latch (1) 1. writing affects the data regi ster, but does not affect input. 1 output latch latch address: $0011 bit 7654321bit 0 read: write: see note pdib3 pdib2 see note reset: 000000 = unimplemented note: these pulldown devices are permanently enabled when pb5, pb4, pb1 and pb0 are con- figured as inputs. figure 7-9. pulldown register b (pdrb) i/o port electrical characteristics MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 69 7.4 i/o port electrical characteristics table 7-3. i/o port dc electrical characteristics (v dd = 5.0 v) (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ?40 c to +85 c, unless otherwise noted. characteristic symbol min typ (2) 2. typical values reflect average measur ements at midpoint of voltage range, 25 c. max unit current drain per pin i ? ? 25 ma output high voltage (i load = ?2.5 ma) pa4?pa7 (i load = ?5.5 ma) pb2?pb3, pa0?pa3 v oh v dd ?0.8 v dd ?0.8 ? ? ? ? v output low voltage (i load = 10.0 ma) pa0?pa7, pb2?pb3 v ol ??0.8 v input high voltage pa0?pa7, pb2?pb3 v ih 0.7 x v dd ? v dd v input low voltage pa0?pa7, pb2?pb3 v il v ss ? 0.2 x v dd v i/o ports hi-z leakage current pa0?pa7, pb2?pb3 (without individual pulldown activated) i il ?0.2 1 a input pulldown current pa0?pa7, pb2?pb3 (with individual pulldown activated) i il 35 80 200 a table 7-4. i/o port dc electrical characteristics (v dd = 3.3 v) (1) 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = ?40 c to +85 c, unless otherwise noted. characteristic symbol min typ (2) 2. typical values reflect average measur ements at midpoint of voltage range, 25 c. max unit current drain per pin i ? ? 25 ma output high voltage (i load = ?0.8 ma) pa4?pa7 (i load = ?1.5 ma) pa0?pa3, pb2?pb3 v oh v dd ?0.3 v dd ?0.3 ? ? ? ? v output low voltage (i load = 5.0 ma) pa4?pa7 (i load = 3.5 ma) pa0?pa3, pb2?pb3 v ol ? ? ? ? 0.5 0.5 v input high voltage pa0?pa7, pb2?pb3 v ih 0.7 x v dd ? v dd v input low voltage pa0?pa7, pb2?pb3 v il v ss ? 0.2 x v dd v i/o ports hi-z leakage current pa0?pa7, pb2?pb3 (without individual pulldown activated) i il ?0.1 1 a input pulldown current pa0?pa7, pb2?pb3 (with indivi dual pulldown activated) i il 12 30 100 a parallel i/o ports (ports) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 70 freescale semiconductor MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 71 chapter 8 resets and interrupts 8.1 introduction reset initializes the mcu by returning the program counter to a known address and by forcing control and status bits to known states. interrupts temporarily change the sequence of program execution to respond to events that occur during processing. 8.2 resets a reset immediately stops the operation of the instru ction being executed, initializes certain control and status bits, and loads the program counter with a user-defined reset vector address. the following sources can generate a reset: power-on reset (por) circuit reset pin computer operating properly (cop) watchdog illegal address figure 8-1. reset sources dq ck s reset latch internal clock rst to cpu and reset pin v dd peripheral modules illegal address cop watchdog power-on reset resets and interrupts MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 72 freescale semiconductor 8.2.1 powe r-on reset a positive transition on the v dd pin generates a power-on reset. note the power-on reset is strictly for power-up conditions and cannot be used to detect drops in power supply voltage. a 4064-t cyc (internal clock cycle) delay after the oscillator becomes active allows the clock generator to stabilize. if any reset source is active at the end of this delay, the mcu remains in the reset condition until all reset sources are inactive. figure 8-2. power-on reset timing 8.2.2 external reset a logic 0 applied to the reset pin for 1 1/2 t cyc generates an external reset. a schmitt trigger senses the logic level at the reset pin. figure 8-3. external reset timing table 8-1. external reset timing characteristic symbol min max unit reset pulse width t rl 1.5 ? t cyc oscillator stabilization delay (2) v dd osc1 pin internal clock internal address bus notes: internal data bus 1. power-on reset threshold is typically between 1 v and 2 v. 2. 4064 cycles or 128 cycles, dependi ng on state of soscd bit in mor $07fe $07fe $07fe $07fe $07fe $07fe $07ff new pch new pcl (note 1) 3. internal clock, internal address bus, and internal data bus are not available externally. internal clock internal address bus notes: internal data bus $07fe $07fe $07fe $07fe $07ff new pc 1. internal clock, internal address bus, and internal data bus are not available externally. 2. the next rising edge of the internal clock after the rising edge of reset initiates the reset sequence. new pch t rl new pc new pcl dummy op code reset interrupts MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 73 8.2.3 cop watchdog reset a timeout of the cop watchdog generates a cop reset. the cop watchdog is part of a software error detection system and must be cleared periodically to start a new timeout period. to clear the cop watchdog and prevent a cop reset, write a logic 0 to bit 0 (copc) of the cop register at location $07f0. 8.2.4 illegal address reset an opcode fetch from an address not in ram or eprom generates a reset. 8.3 interrupts the following sources can generate interrupts: swi instruction external interrupt pins ?irq /v pp pin ? pa0?pa3 pins timer ? real-time interrupt flag (rtif) ? timer overflow flag (tof) an interrupt temporarily stops the program sequence to process a particular event. an interrupt does not stop the operation of the instruction being executed, but takes effect when the current instruction completes its execution. interrupt processing automatically saves the cpu registers on the stack and loads the program counter with a user-defined interrupt vector address. 8.3.1 software interrupt the software interrupt (swi) instruction causes a non-maskable interrupt. 8.3.2 external interrupt an interrupt signal on the irq /v pp pin latches an external interrupt request. when the cpu completes its current instruction, it tests the irq latch. if the irq latch is set, the cpu then tests the i bit in the condition code register. if the i bit is clear, the cpu then begins the interrupt sequence. the cpu clears the irq latch during interrupt processing, so that another interrupt signal on the irq /v pp pin can latch another interrupt request during the interru pt service routine. as soon as the i bit is cleared during the return from interrupt, the cpu can recognize the new interrupt request. figure 8-4 shows the irq /v pp pin interrupt logic. setting the i bit in the condition code re gister disables external interrupts. the port a external interrupt bit (pirq) in the mask option register enables pins pa0?pa3 to function as external interrupt pins. the external interrupt sensitivity bit (level) in the mask option register cont rols interrupt triggering sensitivity of external interrupt pins. the irq /v pp pin can be negative-edge triggered only or negative-edge and low-level triggered. port a external interrupt pins can be positive-edge triggered only or both positive-edge and high-level triggered. the level-sensitive triggering option allows multiple external interrupt sources to be wire-ored to an external interrupt pin. an external interrupt request, shown in figure 8-5 , is latched as long as any source is holding an external interrupt pin low. resets and interrupts MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 74 freescale semiconductor figure 8-4. external interrupt logic figure 8-5. external interrupt timing table 8-2. external interrupt timing (v dd = 5.0 vdc) (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ?40 c to +85 c, unless otherwise noted. characteristic symbol min max unit interrupt pulse width low (edge-triggered) t ilih 125 ? ns interrupt pulse period t ilil note (2) 2. the minimum t ilil should not be less than the number of interrupt se rvice routine cycles plus 19 t cyc . ? t cyc table 8-3. external interrupt timing (v dd = 3.3 vdc) (1) 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = ?40 c to +85 c unless otherwise noted. characteristic symbol min max unit interrupt pulse width low (edge-triggered) t ilih 250 ? ns interrupt pulse period t ilil note (2) 2. the minimum t ilil should not be less than the number of interrupt service routine cycles plus 19 t cyc . ? t cyc pirq level-sensitive trigger pa3 pa2 pa1 irq pa0 v dd (mor level bit) reset irq vector fetch external interrupt request (mor) to bih & bil instruction processing irqf irqr irqe dq ck irq clr latch irq t ilih t ilil t ilih ext. int. pin ext. int. pin 1 ext. int. pin n . . . (internal) interrupts MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 75 8.3.3 timer interrupts the timer can generate the following interrupt requests: real time timer overflow setting the i bit in the condition code register disables timer interrupts. 8.3.3.1 real-time interrupt a real-time interrupt occurs if the real-time interrupt flag, rtif, becomes set while the real-time interrupt enable bit, rtie, is also set. rtif and rtie are in the timer status and control register. 8.3.3.2 timer overflow interrupt a timer overflow interrupt request occurs if the ti mer overflow flag, tof, becomes set while the timer overflow interrupt enable bit, toie, is also set. tof and toie are in the timer status and control register. 8.3.4 interrupt processing the cpu takes the following actions to begin servicing an interrupt: stores the cpu registers on the stack in the order shown in figure 8-6 sets the i bit in the condition code register to prevent further interrupts loads the program counter with the contents of the appropriate interrupt vector locations: ? $07fc and $07fd (software interrupt vector) ? $07fa and $07fb (external interrupt vector) ? $07f8 and $07f9 (timer interrupt vector) the return-from-interrupt (rti) instruction causes the cpu to recover the cpu registers from the stack as shown in figure 8-6 . resets and interrupts MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 76 freescale semiconductor figure 8-6. interrupt stacking order table 8-4. reset/interrupt vector addresses function source local mask global mask priority (1 = highest) vector address reset power-on reset pin cop watchdog (1) illegal address 1. the cop watchdog is programmab le in the mask option register. none none 1 $07fe ? $07ff software interrupt (swi) user code none none same priority as instruction $07fc ? $07fd external interrupt irq /v pp pin irqe i bit 2 $07fa ? $07fb timer interrupts rtif bit tof bit rtie bit toie bit i bit 3 $07f8 ? $07f9 condition code register $00c0 (bottom of stack) $00c1 $00c2 accumulator index register program counter (high byte) program counter (low byte) $00fd $00fe $00ff (top of stack) 1 2 3 4 5 5 4 3 2 1 unstacking order stacking order interrupts MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 77 figure 8-7. interrupt flowchart external interrupt? i bit set? timer interrupt? fetch next instruction. swi instruction? rti instruction? stack pc, x, a, ccr. set i bit. load pc with interrupt vector. yes yes yes yes yes unstack ccr, a, x, pc. execute instruction. clear irq latch. no no no no no from reset resets and interrupts MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 78 freescale semiconductor MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 79 chapter 9 multifunction timer module 9.1 introduction the multifunction timer provides a timing reference with programmable real-time interrupt capability. figure 9-2 shows the timer organization. 9.2 features features of the multifunction timer include: timer overflow four selectable interrupt rates computer operating properly (cop) watchdog timer 9.3 operation a 15-stage ripple counter, preceded by a pr escaler that divides the internal clock signal by four, provides the timing reference for the timer functions. the value of the first eight timer stages can be read at any time by accessing the timer counter register at ad dress $0009. a timer overflow function at the eighth stage allows a timer interrupt every 1024 internal clock cycles. the next four stages lead to the real-time interrupt (rti) circuit. the rt1 and rt0 bits in the timer status and control register at address $0008 allow a time r interrupt every 16,384, 32,768, 65,536, or 131,072 clock cycles. the last four stages drive the select able cop system. for information on the cop, refer to chapter 3 computer operating properly module (cop) . addr. register name bit 7 6 5 4 3 2 1 bit 0 $0008 timer status and control register (tscr) see page 81. read: tof rtif toie rtie 00 rt1 rt0 write: tofr rtifr reset:00000011 $0009 timer counter register (tcr) see page 82. read: tmr7 tmr6 tmr5 tmr4 tmr3 tmr2 tmr1 tmr0 write: reset:00000000 = unimplemented figure 9-1. i/o register summary multifunction timer module MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 80 freescale semiconductor figure 9-2. multifunction timer block diagram 9.4 interrupts the following timer sources can generate interrupts: timer overflow flag (tof) ? the tof bit is set when the first eight stages of the counter roll over from $ff to $00. the timer overflow interrupt enable bit, toie, enables tof interrupt requests. real-time interrupt flag (rtif) ? the rtif bit is set when the selected rti output becomes active. the real-time interrupt enable bit, rtie, enables rtif interrupt requests. clear cop timer timer counter register bits [0:7] of 15-stage overflow internal clock (xtal 2) timer status/control register tof rtif toie rtie tofr rtifr rt1 rt0 rti rate select 2 2 2 2 2 2 2 bits [8:14] of 15-stage ripple counter 8 s r q interrupt request cop reset internal data bus reset ripple counter reset reset reset 4 i/o registers MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 81 9.5 i/o registers the following registers control and monitor the timer operation: timer status and control register (tscr) timer counter register (tcr) 9.5.1 timer status and control register the read/write timer status and control r egister performs the following functions: flags timer interrupts enables timer interrupts resets timer interrupt flags selects real-time interrupt rates tof ? timer overflow flag this read-only flag becomes set when the first eight stages of the counter roll over from $ff to $00. tof generates a timer overflow interrupt request if toie is also set. clear tof by writing a logic 1 to the tofr bit. writing to tof has no effect. reset clears tof. rtif ? real-time interrupt flag this read-only flag becomes set when the selected rti output becomes active. rtif generates a real-time interrupt request if rtie is also set. clear rtif by writing a logic 1 to the rtifr bit. writing to rtif has no effect. reset clears rtif. toie ? timer overflow interrupt enable bit this read/write bit enables timer overflow interrupts. reset clears toie. 1 = timer overflow interrupts enabled 0 = timer overflow interrupts disabled rtie ? real-time interrupt enable bit this read/write bit enables real-time interrupts. reset clears rtie. 1 = real-time interrupts enabled 0 = real-time interrupts disabled tofr ? timer overflow flag reset bit writing a logic 1 to this write-only bit clears the tof bit. tofr always reads as logic 0. reset clears tofr. rtifr ? real-time interrupt flag reset bit writing a logic 1 to this write-only bit clears the rt if bit. rtifr always reads as logic 0. reset clears rtifr. address: $0008 bit 7654321bit 0 read: tof rtif toie rtie 00 rt1 rt0 write: tofr rtifr reset:00000011 = unimplemented figure 9-3. timer status and control register (tscr) multifunction timer module MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 82 freescale semiconductor rt1 and rt0 ? real-time interrupt select bits these read/write bits select one of four real-time interrupt rates, as shown in table 9-1 . because the selected rti output drives the cop watchdog, changing the real-time interrupt rate also changes the counting rate of the cop watchdog. reset sets rt1 and rt0. note changing rt1 and rt0 when a cop ti meout is imminent can cause a real-time interrupt request to be mi ssed or an additional real-time interrupt request to be generated. to prevent this occurrence, clear the cop timer before changing rt1 and rt0. 9.5.2 timer counter register a 15-stage ripple counter is the core of the timer. the value of the first eight stages is readable at any time from the read-only timer counter register shown in figure 9-4 . power-on clears the entire counter chain and the inte rnal clock begins clocking the counter. after 4064 cycles (or 16 cycles if the soscd bit in the mask op tion register is set), the power-on reset circuit is released, clearing the counter again and allowing the mcu to come out of reset. a timer overflow function at the eighth counter stage allows a timer interrupt every 1024 internal clock cycles. table 9-1. real-time interrupt rate selection rt1:rt0 rti rate rti period (f op = 2 mhz) cop timeout period (?0/+1 rti period) minimum cop timeout period (f op = 2 mhz) 00 f op 2 14 8.2 ms 8 x rti period 65.5 ms 01 f op 2 15 16.4 ms 8 x rti period 131.1 ms 10 f op 2 16 32.8 ms 8 x rti period 262.1 ms 11 f op 2 17 65.5 ms 8 x rti period 524.3 ms address: $0009 bit 7654321bit 0 read: tcr7 tcr6 tcr5 tcr4 tcr3 tcr2 tcr1 tcr0 write: reset:00000000 = unimplemented figure 9-4. timer counter register (tcr) low-power modes MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 83 9.6 low-power modes the stop and wait instructions put the mcu in low power-consumption standby states. 9.6.1 stop mode the stop instruction has the following effects on the timer: clears the timer counter clears interrupt flags (tof and rtif) and interrupt enable bits (tofe and rtie) in tscr, removing any pending timer interrupt requests and disabling further timer interrupts 9.6.2 wait mode the timer remains active after a wait instruction. any enabled timer interrupt request can bring the mcu out of wait mode. multifunction timer module MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 84 freescale semiconductor MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 85 chapter 10 electrical specifications 10.1 maximum ratings maximum ratings are the extreme limits to which t he microcontroller unit (mcu) can be exposed without permanently damaging it. note this device is not guaranteed to operate properly at the maximum ratings. for guaranteed operating conditions, refer to 10.5 5.0-v dc electrical characteristics and 10.6 3.3-v dc electrical characteristics 10.2 operating temperature range 10.3 thermal characteristics table 10-1. maximum ratings (1) 1. voltages are referenced to v ss . rating symbol value unit supply voltage v dd ?0.3 to +7.0 v current drain per pin (excluding v dd , v ss ) i25ma input voltage v in v ss ? 0.3 to v dd + 0.3 v irq /v pp pin v pp v ss ? 0.3 to 2 x v dd + 0.3 v storage temperature range t stg ?65 to +150 c package type symbol value (t l to t h ) unit MC68HC705KJ1c (1) p (2) , cdw (3) , cs (4) 1. c = extended temperature range 2. p = plastic dual in-line package (pdip) 3. dw = small outline integrated circuit (soic) 4. s = ceramic dip (cerdip) t a ?40 to +85 c characteristic symbol value unit thermal resistance MC68HC705KJ1p (1) MC68HC705KJ1dw (2) MC68HC705KJ1s (3) 1. p = plastic dual in-line package (pdip) 2. dw = small outline integrated circuit (soic) 3. s = ceramic dip (cerdip) ja 60 c/w electrical specifications MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 86 freescale semiconductor 10.4 power considerations the average chip junction temperature, t j , in c can be obtained from: (1) where: t a = ambient temperature in c ja = package thermal resistance, junction to ambient in c/w p d = p int + p i/o p int = i cc v cc = chip internal power dissipation p i/o = power dissipation on input and output pins (user-determined) for most applications, p i/o p int and can be neglected. ignoring p i/o , the relationship between p d and t j is approximately: (2) solving equations (1) and (2) for k gives: (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . t j t a p d ja () + = p d k t j 273 c + ----------------------------------- = = p d x (t a + 273c) + j a x (p d ) 5.0-v dc electrical characteristics MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 87 10.5 5.0-v dc electrical characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ?40 c to +85 c, unless otherwise noted. symbol min typ (2) 2. typical values at midpoint of voltage range, 25 c only max unit output high voltage (i load = ?2.5 ma) pa4?pa7 (i load = ?5.5 ma) pb2?pb3, pa0?pa3 v oh v dd ?0.8 v dd ?0.8 ? ? ? ? v output low voltage (8) (i load = 10.0 ma) pa0?pa7, pb2?pb3 v ol ??0.8v input high voltage pa0?pa7, pb2?pb3, irq /v pp , reset , osc1 v ih 0.7 v dd ? v dd v input low voltage pa0?pa7, pb2?pb3, irq /v pp , reset , osc1 v il v ss ? 0.2 v dd v supply current (f op = 2.1 mhz; f osc = 4.2 mhz) run mode (3) wait mode (4) stop mode (5) 3. run mode i dd is measured using external square wave clock source; all inputs 0.2 v from rail; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2. 4. wait mode i dd : only timer system active. wait mode is affected linearly by osc2 capacitance. wait mode is measured with all ports config ured as inputs; v il = 0.2 v; v ih = v dd ? 0.2 v. wait mode i dd is measured using external square wave clock source; all inputs 0.2 v from rail; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2. 5. stop mode i dd is measured with osc1 = v ss . stop mode i dd is measured with all ports configured as inputs; v il = 0.2 v; v ih = v dd ? 0.2 v. i dd ? ? ? 4.0 1.0 0.1 6.0 2.8 5.0 ma ma a supply current (f op = 4.0 mhz; f osc = 8.0 mhz) run mode (3) wait mode (4) stop mode (5) i dd ? ? ? 5.2 1.1 0.1 7.0 3.3 5.0 ma ma a i/o ports hi-z leakage current pa0?pa7, pb2?pb3 (without individual pulldown activated) i il ?0.2 1 a input pulldown current pa0?pa7, pb2?pb3 (with individual pulldown activated) i il 35 80 200 a input pullup current reset i il ?15 ?35 ?85 a input current (6) reset , irq /v pp , osc1 6. only input high current rated to +1 a on reset . i in ?0.2 1 a capacitance ports (as inputs or outputs) reset , irq , osc1, osc2 c out c in ? ? ? ? 12 8 pf crystal/ceramic resonator oscill ator mode internal resistor osc1 to osc2 (7) 7. the r osc value selected for rc oscillator versions of this device is unspecified. 8. maximum current drain for all i/o pins combined should not exceed 100 ma. r osc 1.0 2.0 3.0 m ? electrical specifications MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 88 freescale semiconductor 10.6 3.3-v dc electrical characteristics characteristic (1) 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = ?40 c to +85 c, unless otherwise noted. symbol min typ (2) 2. typical values at midpoint of voltage range, 25 c only max unit output high voltage (i load = ?0.8 ma) pa4?pa7 (i load = ?1.5 ma) pa0?pa3, pb2?pb3 v oh v dd ?0.3 v dd ?0.3 ? ? ? ? v output low voltage (i load = 5.0 ma) pa4?pa7 (i load = 3.5 ma) pa0?pa3, pb2?pb3 v ol ? ? ? ? 0.5 0.5 v input high voltage pa0?pa7, pb2?pb3, irq /v pp , reset , osc1 v ih 0.7 v dd ? v dd v input low voltage pa0?pa7, pb2?pb3, irq /v pp , reset , osc1 v il v ss ? 0.2 v dd v supply current (f op = 1.0 mhz; f osc = 2.0 mhz) run mode (3) wait mode (4) stop mode (5) 3. run mode i dd is measured using external square wave clock source; all inputs 0.2 v from rail; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2. 4. wait mode i dd : only timer system active. wait mode is affected linearly by osc2 capacitance. wait mode is measured with all ports config ured as inputs; v il = 0.2 v; v ih = v dd ? 0.2 v. wait mode i dd is measured using external square wave clock source; all inputs 0.2 v from rail; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2. 5. stop mode i dd is measured with osc1 = v ss . stop mode i dd is measured with all ports configured as inputs; v il = 0.2 v; v ih = v dd ? 0.2 v. i dd ? ? ? 1.2 0.3 0.1 2.5 0.8 5.0 ma ma a supply current (f op = 2.1 mhz; f osc = 4.2 mhz) run mode (3) wait mode (4) stop mode (5) i dd ? ? ? 1.4 0.3 0.1 3.0 1.0 5.0 ma ma a i/o ports hi-z leakage current pa0?pa7, pb2?pb3 (without individual pulldown activated) i il ?0.1 1 a input pulldown current pa0?pa7, pb2?pb3 (with individual pulldown activated) i il 12 30 100 a input pullup current reset i il ?10 ?25 ?45 a input current (6) reset , irq /v pp , osc1 6. only input high current rated to +1 a on reset . i in ?0.1 1 a capacitance ports (as inputs or outputs) reset , irq /v pp , osc1, osc2 c out c in ? ? ? ? 12 8 pf crystal/ceramic resonator oscill ator mode internal resistor osc1 to osc2 (7) 7. the r osc value selected for rc oscillator versio ns of this device is unspecified. r osc 1.0 2.0 3.0 m ? driver characteristics MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 89 10.7 driver characteristics figure 10-1. pa4?pa7 typical high-side driver characteristics figure 10-2. pa0?pa3 and pb2?pb3 typical high-side driver characteristics notes: 1. at v dd = 5.0 v, devices are specified and tested for (v dd ? v oh ) 800 mv @ i oh = ?2.5 ma. 2. at v dd = 3.3 v, devices are specified and tested for (v dd ? v oh ) 300 mv @ i oh = ?0.8 ma. 0 100 200 300 400 500 600 700 800 0?2?4?6?8?10 i oh (ma) v dd ? v oh (mv) ?40 c 85 c 25 c v dd = 3.3 v 0 100 200 300 400 500 600 700 800 0?2?4?6?8?10 i oh (ma) v dd ? v oh (mv) ?40 c 85 c 25 c v dd = 5.0 v notes: 1. at v dd = 5.0 v, devices are specified and tested for (v dd ? v oh ) 800 mv @ i oh = ?5.5 ma. 2. at v dd = 3.3 v, devices are specified and tested for (v dd ? v oh ) 300 mv @ i oh = ?1.5 ma. 0 100 200 300 400 500 600 700 800 0 ?2 ?4 ?6 ?8 ?10 i oh (ma) v dd ? v oh (mv) ?40 c 25 c v dd = 3.3 v 85 c 0 100 200 300 400 500 600 700 800 0 ?2?4 ?6?8?10 i oh (ma) v dd ? v oh (mv) ?40 c 85 c 25 c v dd = 5.0 v electrical specifications MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 90 freescale semiconductor figure 10-3. pa4?pa7 typical low-side driver characteristics figure 10-4. pa0?pa3 and pb2?pb3 typical low-side driver characteristics notes: 1. at v dd = 5.0 v, devices are specified and tested for v ol 800 mv @ i ol = 10.0 ma. 2. at v dd = 3.3 v, devices are specified and tested for v ol 500 mv @ i ol = 5.0 ma. 0 100 200 300 400 500 600 700 800 0 1020 3040 50 ?40 c 25 c 85 c v dd = 3.3 v 0 100 200 300 400 500 600 700 800 0 1020 3040 50 ?40 c 25 c i ol (ma) v ol (mv) 85 c v dd = 5.0 v v ol (mv) i ol (ma) notes: 1. at v dd = 5.0 v, devices are specified and tested for v ol 800 mv @ i ol = 10.0 ma. 2. at v dd = 3.3 v, devices are specified and tested for v ol 500 mv @ i ol = 3.5 ma. 0 100 200 300 400 500 600 700 800 0102030 ?40 c 25 c 85 c v dd = 3.3 v 0 100 200 300 400 500 600 700 800 0102030 ?40 c 25 c 85 c v dd = 5.0 v v ol (mv) v ol (mv) i ol (ma) i ol (ma) typical supply currents MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 91 10.8 typical supply currents figure 10-5. typical operating i dd (25 c) figure 10-6. typical wait mode i dd (25 c) 6.0 ma 5.0 ma 4.0 ma 3.0 ma 2.0 ma 1.0 ma 0 0 1.0 mhz 2.0 mhz 3.0 mhz 4.0 mhz 3.0 v 4.5 v 3.6 v 5.5 v s u p p l y c u r r e n t ( i d d ) internal operating frequency (f op ) notes: 1. at v dd = 5.0 v, devices are specified and tested for i dd 7.0 ma @ f op = 4.0 mhz. 2. at v dd = 3.3 v, devices are specified and tested for i dd 4.25 ma @ f op = 2.1 mhz. see note 1 see note 2 7.0 ma 700 a 600 a 500 a 400 a 300 a 200 a 100 a 0 0 1.0 mhz 2.0 mhz 3.0 mhz 4.0 mhz 3.0 v 4.5 v 3.6 v 5.5 v s u p p l y c u r r e n t ( i d d ) internal operating frequency (f op ) notes: 1. at v dd = 5.0 v, devices are specified and tested for i dd 3.25 ma @ f op = 4.0 mhz. 2. at v dd = 3.3 v, devices are specified and tested for i dd 1.75 ma @ f op = 2.1 mhz. see note 1 see note 2 electrical specifications MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 92 freescale semiconductor 10.9 eprom programm ing characteristics 10.10 control timing characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ? 40 c to +85 c, unless otherwise noted. symbol min typ max unit programming voltage irq /v pp v pp 16.0 16.5 17.0 v programming current irq /v pp i pp ?| 3.0 10.0 ma programming time per array byte mor t epgm t mpgm 4 4 ? ? ? ? ms table 10-2. control timing (v dd = 5.0 vdc) (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ? 40 c to +85 c, unless otherwise noted. characteristic symbol min max unit oscillator frequency crystal oscillator option external clock source f osc ? dc 8.0 8.0 mhz internal operating frequency (f osc 2) crystal oscillator external clock f op ? dc 4.0 4.0 mhz cycle time (1 f op )t cyc 250 ? ns reset pulse width low t rl 1.5 ? t cyc irq interrupt pulse width low (edge-triggered) t ilih 1.5 ? t cyc irq interrupt pulse width low (edge- and level-triggered) t ilil 1.5 note (2) 2. the maximum width t ilil or t ilih should not be more than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc or the interrupt service routine will be re-entered. t cyc pa0?pa3 interrupt pulse width high (edge-triggered) t ihil 1.5 ? t cyc pa0?pa3 interrupt pulse width (edge- and level-triggered) t ihih 1.5 note (2) t cyc osc1 pulse width t oh , t ol 100 ? ns control timing MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 93 figure 10-7. external interrupt timing table 10-3. control timing (v dd = 3.3 vdc) (1) 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = ? 40 c to +85 c, unless otherwise noted. characteristic symbol min max unit oscillator frequency crystal oscillator option external clock source f osc ? dc 4.2 4.2 mhz internal operating frequency (f osc 2) crystal oscillator external clock f op ? dc 2.1 2.1 mhz cycle time (1 f op )t cyc 476 ? ns reset pulse width low t rl 1.5 ? t cyc irq interrupt pulse width low (edge-triggered) t ilih 1.5 ? t cyc irq interrupt pulse width low (edge- and level-triggered) t ilil 1.5 note (2) 2. the maximum width t ilil or t ilih should not be more than the nu mber of cycles it takes to execute the interrupt service routine plus 19 t cyc or the interrupt service routine will be re-entered. t cyc pa0?pa3 interrupt pulse width high (edge-triggered) t ihil 1.5 ? t cyc pa0?pa3 interrupt pulse width (edge- and level-triggered) t ihih 1.5 note (2) t cyc osc1 pulse width t oh , t ol 200 ? ns irq t ilih t ilil t ilih irq pin irq 1 irq n . . . (internal) electrical specifications MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 94 freescale semiconductor figure 10-8. stop mode recovery timing figure 10-9. power-on reset timing t ilih oscillator stabilization delay (5) osc (note 1) t rl reset irq (note 2) irq (note 3) internal clock internal address bus notes: 1. internal clocking from osc1 pin 2. edge-triggered external interrupt mask option 3. edge- and level-triggered external interrupt mask option 4. reset vector shown as example reset or interrupt vector fetch 07fe 07fe 07fe 07fe 07fe 07ff (note 4) 5. 4064 t cyc or 128 t cyc , depending on the state of soscd bit in mor 07fe oscillator stabilization delay (3) v dd osc1 pin internal clock internal address bus notes: internal data bus 07fe 07fe 07fe 07fe 07fe 07ff (note 1) 1. power-on reset threshold is typically between 1 v and 2 v. 2. internal clock, internal address bus, and internal data bus are not available externally. new pch new pcl 3. 4064 t cyc or 128 t cyc depending on the state of soscd bit in mor control timing MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 95 figure 10-10. external reset timing internal clock internal address bus notes: internal data bus 07fe 07fe 07fe 07fe 07ff new pc 1. internal clock, internal address bus, and in ternal data bus are not available externally. 2. the next rising edge of the internal clock after the rising edge of reset initiates the reset sequence. new pch t rl new pc new pcl dummy op code electrical specifications MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 96 freescale semiconductor MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 97 chapter 11 ordering information and mechanical specifications 11.1 introduction the mc68hc705j1a, the rc oscillator, a nd low-speed option devices described in appendix a mc68hrc705kj1 and appendix b mc68hlc705kj1 are available in these packages: 648 ? plastic dual in-line package (pdip) 751g ? small outline integrated circuit (soic) 620a ? ceramic dip (cerdip) (windowed) this section contains ordering information and mechan ical specifications for the available package types. 11.2 mcu order numbers table 11-1 lists the mc order numbers. table 11-1. order numbers (1) 1. refer to appendix a mc68hrc705kj1 and appendix b mc68hlc705kj1 for ordering information on optional low-speed and resi stor-capacitor oscillator devices. package type case outline pin count operating temperature order number pdip 648 16 ?40 to +85 c MC68HC705KJ1c (2) 2. c = extended temperature range soic 751g 16 ?40 to +85 c MC68HC705KJ1cdw (3) 3. dw = small outline integrated circuit (soic) cerdip 620a 16 ?40 to +85 c MC68HC705KJ1cs (4) 4. s = ceramic dual in-line package (cerdip) ordering information and mechanical specifications MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 98 freescale semiconductor 11.3 16-pin pdip ? case #648 11.4 16-pin soic ? case #751g notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. style 1: pin 1. cathode style 2: pin 1. common drain ?a? b f c s h g d j l m 16 pl seating 18 9 16 k plane ?t? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 f j dim min max min max inches millimeters a 10.15 10.45 0.400 0.411 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 m b m 0.010 (0.25) -a- -b- p 8x g 14x d 16x seating plane -t- s a m 0.010 (0.25) b s t 16 9 8 1 r x 45 m c k 16-pin cerdip ? case #620a MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 99 11.5 16-pin cerdip ? case #620a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension f may narrow to 0.76 (0.030) where the lead enters the ceramic body. style 1: pin 1. cathode 2. cathode 3. cathode 4. cathode 5. cathode 6. cathode 7. cathode 8. cathode 9. anode 10. anode 11 anode f e n k c seating plane a m 0.25 (0.010) t m l dim min max min max millimeters inches a 0.750 0.785 19.05 19.93 b 0.240 0.295 6.10 7.49 c ??? 0.200 ??? 5.08 d 0.015 0.020 0.39 0.50 e 0.050 bsc 1.27 bsc f 0.055 0.065 1.40 1.65 g 0.100 bsc 2.54 bsc h 0.008 0.015 0.21 0.38 k 0.125 0.170 3.18 4.31 l 0.300 bsc 7.62 bsc m 0 15 0 15 n 0.020 0.040 0.51 1.01 a b a b 16 1 9 8 g 16x d b m 0.25 (0.010) t t 16x j ordering information and mechanical specifications MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 100 freescale semiconductor MC68HC705KJ1 ? mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 101 appendix a mc68hrc705kj1 a.1 introduction this appendix introd uces the mc68hrc705kj1, a resistor-capacit or (rc) oscillator mask option version of the MC68HC705KJ1. all of the information in MC68HC705KJ1 technical data applies to the mc68hrc705kj1 with the exceptions given in this appendix. a.2 rc oscillator connections for greater cost reduction, the rc oscillator mask option allows the configuration shown in figure a-1 to drive the on-chip oscillator. mount the rc components as close as possible to the pins for startup stabilization and to minimize output distortion. figure a-1. rc oscillator connections note the optional internal resistor is not recommended for configurations that use the rc oscillator connections as shown in figure a-1 . for such configurations, the oscillator internal resistor (oscres) bit of the mask option register should be programmed to a logic 0. mcu v dd v ss c1 c2 osc1 osc2 r osc1 osc2 r mc68hrc705kj1 MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 102 freescale semiconductor a.3 typical internal operating frequency for rc oscillator option figure a-2 shows typical internal operating frequencies at 25 c for the rc oscillator option. note tolerance for resistance is 50%. when selecting resistor size, consider the tolerance to ensure that the resulting oscillator frequency does not exceed the maximum operating frequency. figure a-2. typical internal operating frequency for various v dd at 25 c ? rc oscillator option only 0.1 1 10 1 10 100 1000 resistance (k ? rc oscillator connections (no external resistor) MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 103 a.4 rc oscillator connectio ns (no external resistor) for maximum cost reduction, the rc os cillator mask connections shown in figure a-3 allow the on-chip oscillator to be driven with no external components. this can be accomplished by programming the oscillator internal resistor (oscres) bit in the mask option register to a logic 1. when programming the oscres bit for the mc68hrc705kj1, an internal resistor is selected which yields typical internal oscillator frequencies as shown in figure a-4 . the internal resistance for th is device is different than the resistance of the selectable internal resistor on the MC68HC705KJ1 and the mc68hrc705kj1 devices. figure a-3. rc oscillator connections (no external resistor) mcu v dd v ss c1 c2 osc1 osc2 osc1 osc2 r (external connections left open) mc68hrc705kj1 MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 104 freescale semiconductor a.5 typical internal operatin g frequency versus temperature (no external resistor) figure a-4. typical internal operating frequency versus temperature (oscres bit = 1) note due to process variations, operating voltages, and temperature requirements, the internal resistance and tolerance are unspecified. typically for a given voltage and te mperature, the frequency should not vary more than 500 khz. however, this data is not guaranteed. it is the user?s responsibility to ensure that the resulting internal operating frequency meets user?s requirements. a.6 package types and order numbers table a-1. mc68hrc705kj1 (rc oscillator option) order numbers (1) 1. refer to chapter 11 ordering informati on and mechanical specifications for standard part ordering information. package type case outline pin count operating temperature order number pdip 648 16 ?40 to +85 c mc68hrc705kj1c (2) p (3) 2. c = extended temperature range 3. p = plastic dual in-line package (pdip) soic 751g 16 ?40 to +85 c mc68hrc705kj1cdw (4) 4. dw = small outline integrated circuit (soic) cerdip 620a 16 ?40 to +85 c mc68hrc705kj1cs (5) 5. s = ceramic dual in-line package (cerdip) frequency (mhz) temperature ( MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 freescale semiconductor 105 appendix b mc68hlc705kj1 b.1 introduction this appendix introduces the mc68hlc705kj1, a low-frequency version of the MC68HC705KJ1 optimized for 32-khz oscillators. all of the information in MC68HC705KJ1 technical data applies to the mc68hlc705kj1 with the exceptions given in this appendix. b.2 dc electrical characteristics figure b-1. crystal connections note supply current is impacted by crystal type and external components.since each crystal has its own characteristic s, the user should consult the crystal manufacturer for appropriate va lues for external components. table b-1. dc electrical characteristics (v dd = 5 v) characteristic symbol min typ max unit supply current (f op = 16.0 khz, f osc = 32.0 khz) run wait i dd ? ? 45 20 60 30 a table b-2. dc electrical characteristics (v dd = 3.3 v) characteristic symbol min typ max unit supply current (f op = 16.0 khz, f osc = 32.0 khz) run wait i dd ? ? 25 10 35 15 a mcu osc1 osc2 r p 32 khz c l c l r s mc68hlc705kj1 MC68HC705KJ1 mc68hrc705kj1 mc68hlc705kj1 data sheet, rev. 4.1 106 freescale semiconductor b.3 package types and order numbers table b-3. mc68hlc705kj1 (low frequency) order numbers (1) 1. refer to chapter 11 ordering informati on and mechanical specifications for standard part ordering information. package type case outline pin count operating temperature order number pdip 648 16 ?40 to +85 c mc68hlc705kj1c (2) p 2. c = extended temperature range soic 751g 16 ?40 to +85 c mc68hlc705kj1cdw (3) 3. dw = small outline integrated circuit (soic) cerdip 620a 16 ?40 to +85 c mc68hlc705kj1cs (4) 4. s = ceramic dual in-line package (cerdip) how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclai ms any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data shee ts and/or specificati ons can and do vary in different applications and actual perfo rmance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2005. all rights reserved. MC68HC705KJ1 rev. 4.1, 07/2005 |
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